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公开(公告)号：US08963753B2
公开(公告)日：2015-02-24
申请号：US13898420
申请日：2013-05-20
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
Abstract: An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.
Abstract translation: 过采样A / D转换器包括：第一滤波器，包括第一电阻元件，第一电容元件，第二电阻元件，运算放大器和第二电容元件; 接收第一滤波器的输出的第二滤波器; 第三滤波器，包括第三电阻元件，第三电容元件和第四电阻元件; 量化器，接收第三滤波器的输出并产生数字信号; 以及将数字信号转换成模拟电流信号的D / A转换器。 D / A转换器将产生的模拟电流信号输入到运算放大器的反相输入端。
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公开(公告)号：US08941526B2
公开(公告)日：2015-01-27
申请号：US14447315
申请日：2014-07-30
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Masao Takayama , Takuji Miki
CPC classification number: G06G7/184 , H03H19/004 , H03K3/0315 , H03M3/02
Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.
Abstract translation: 时间积分器集成了由两个信号之间的相位差表示的时间轴信息。 时间积分器包括：脉冲发生电路，被配置为将两个输入信号的边沿之间的时间差转换为两个脉冲信号的脉冲宽度之间的差，并输出两个脉冲信号，具有由两个脉冲变化的负载特性的负载电路 信号和耦合到负载电路的振荡电路，并且根据负载电路的负载特性使振荡频率发生变化。 作为时间积分的结果输出振荡电路的输出。
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公开(公告)号：US08890741B2
公开(公告)日：2014-11-18
申请号：US13770871
申请日：2013-02-19
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Masao Takayama , Takuji Miki
CPC classification number: H03M1/50 , H03M1/1215
Abstract: An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner.
Abstract translation: 提供了与模拟电路的特性变化无关的具有高精度和高吞吐量的A / D转换器。 A / D转换器包括电压 - 时间转换器，其被配置为与采样时钟信号同步并将输入模拟电压转换为两个信号之间的时间差，并且多个时间 - 数字转换器被配置为将 两个信号之间的时差就是一个数字值。 多个时间 - 数字转换器以交错的方式工作。
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公开(公告)号：US09024793B2
公开(公告)日：2015-05-05
申请号：US14172718
申请日：2014-02-04
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Masao Takayama
CPC classification number: H03M1/50 , G04F10/005 , H03K5/153
Abstract: An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.
Abstract translation: 过采样时间 - 数字转换器包括产生两个脉冲信号的输入脉冲产生电路，产生两个脉冲信号的参考脉冲产生电路，交换两个脉冲信号的交换电路，选择输入脉冲发生电路或 交换电路，根据多路复用器的输出输出两个脉冲电流的时间到电流转换电路，其输入和输出端子接收两个脉冲电流的电流镜电路;积分电路，其在脉冲电流之间积分差分电流 连接到电流镜电路的输出端和电流镜电路的输出电流，以及将积分电路的输出信号与阈值电压进行比较的比较电路。 将比较电路的输出信号作为控制信号提供给交换电路。
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公开(公告)号：US08981978B2
公开(公告)日：2015-03-17
申请号：US14072743
申请日：2013-11-05
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Kazuo Matsukawa , Yosuke Mitani
CPC classification number: H03M3/454 , H03H11/1252 , H03M3/404 , H03M3/438
Abstract: Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.
Abstract translation: 两个电阻元件和电容元件耦合在运算放大器的第一节点和反相输入端子，运算放大器的输出端子和公共节点之间。 电阻元件和电容元件耦合在第一节点和信号输入端子之间。 两个电容元件和电阻元件耦合在第二节点和反相输入端子，输出端子和公共节点之间。 两个电容元件耦合在第二节点和每个信号输入端和公共节点之间。
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Patent Agency Ranking
6.发明授权Time-to-digital conversion circuit and time-to-digital converter including the same 有权时间 - 数字转换电路和包括其的时间 - 数字转换器公开(公告)号：US08976054B2
公开(公告)日：2015-03-10
申请号：US13942478
申请日：2013-07-15
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Masao Takayama , Takuji Miki
CPC classification number: H03M1/50 , G04F10/005
Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.
Abstract translation: 一种用于将两个输入信号之间的时间差转换成1位数字值并且调节两个输入信号之间的时间差以产生两个输出信号的时间 - 数字转换电路，包括：相位比较器，被配置为比较 两个输入信号彼此产生数字值; 相位选择器，被配置为输出具有前导相位的两个输入信号中的一个作为第一信号，并且具有滞后相位的两个输入信号中的另一个作为第二信号; 以及延迟单元，被配置为以延迟输出第一信号，其中时间 - 数字转换电路输出从延迟单元输出的信号和第二信号作为两个输出信号。
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7.发明授权公开(公告)号：US08937567B2
公开(公告)日：2015-01-20
申请号：US13779366
申请日：2013-02-27
Applicant: Panasonic Corporation
Inventor： Koji Obata , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
CPC classification number: H03M3/50 , H03F3/45076 , H03M3/438
Abstract: A delta-sigma modulator includes: an integrator having an operational amplifier; a quantizer quantizing an output of the integrator; a first D-A converter converting an output of the quantizer to a current signal to provide negative feedback to the operational amplifier; a feedforward path feeding forward an input of the integrator to the quantizer; and a second D-A converter converting the output of the quantizer to a current signal to provide negative feedback to the quantizer. The integrator includes a resistive element having a first end connected to the input of the integrator and a second end connected to an inverting input of the operational amplifier, n capacitive circuits connected in series between the inverting input and an output of the operational amplifier, and (n−1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.
Abstract translation: Δ-Σ调制器包括：具有运算放大器的积分器; 量化器，对积分器的输出进行量化; 将量化器的输出转换为电流信号的第一D-A转换器，以向运算放大器提供负反馈; 前馈路径将积分器的输入馈送到量化器; 以及将量化器的输出转换为电流信号的第二D-A转换器，以向量化器提供负反馈。 积分器包括电阻元件，其电阻元件的第一端连接到积分器的输入端，第二端连接到运算放大器的反相输入端，n个电容电路串联连接在反相输入端和运算放大器的输出端之间，以及 （n-1）个电阻元件，每个电阻元件的第一端连接到电容电路的互连节点，第二端连接到公共节点。
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公开(公告)号：US08896477B2
公开(公告)日：2014-11-25
申请号：US14265148
申请日：2014-04-29
Applicant: Panasonic Corporation
Inventor： Shiro Dosho , Masao Takayama
CPC classification number: G04F10/005 , H03L7/0814 , H03L7/087 , H03L7/18 , H03M1/00 , H03M1/12 , H03M1/18 , H03M2201/4233
Abstract: An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.
Abstract translation: 边沿检测器包括接收环形振荡器的相位信号的触发器，在输入信号的边缘定时取消触发器的复位状态的复位器，以及对触发器的输出信号执行逻辑运算的逻辑运算器， 翻牌 相位状态检测器基于触发器的输出信号来检测在输入信号的边缘定时处发生的环形振荡器的相位状态。 时间 - 数字转换器将输入信号和逻辑运算器的输出信号之间的边沿间隔转换为数字值。 在输入信号的边缘定时处，锁存器锁存计数环形振荡器的输出信号的周期数的计数器的值。 操作者根据锁存器，相位状态检测器和时间 - 数字转换器的输出信号计算接收信号的数字值。
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9.发明授权Time difference adjustment circuit and time-to-digital converter including the same 有权时差调节电路和包括其的时间 - 数字转换器公开(公告)号：US08988269B2
公开(公告)日：2015-03-24
申请号：US14109644
申请日：2013-12-17
Applicant: Panasonic Corporation
Inventor： Shiro Dosho
CPC classification number: H03K5/14 , G04F10/005 , H03K5/26
Abstract: A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors.
Abstract translation: 时差调整电路包括两个触发器电路，延迟电路和复位电路。 延迟电路包括第一极性的第一和第二晶体管以及第二极性的第三和第四晶体管，其中第一和第三晶体管的漏极相互耦合，第二和第四晶体管的漏极相互耦合， 第一晶体管和第三晶体管的漏极和第四晶体管的栅极彼此耦合，输入信号耦合到第一晶体管的栅极，输出信号从第二和第四晶体管的漏极提供，第一 并且第二复位信号分别耦合到第二和第三晶体管的栅极。
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10.发明授权Delta sigma modulator, as well as receiver device and wireless communication device provided with same 有权ΔΣ调制器，以及具有相同的接收机设备和无线通信设备公开(公告)号：US09178530B2
公开(公告)日：2015-11-03
申请号：US14139146
申请日：2013-12-23
Applicant: PANASONIC CORPORATION
Inventor： Yosuke Mitani , Kazuo Matsukawa , Koji Obata , Shiro Dosho
Abstract: A delta sigma modulator includes a filter circuit including an integrator having an operational amplifier; a first addition circuit provided between an output section of the filter circuit and an input section of a quantizer, and including a first resistive element; and a second addition circuit including at least one of a first feedforward circuit including a second resistive element or a first feedback circuit configured to feed back, as an analog signal, a digital output signal having been quantized by the quantizer, to an input section of the quantizer, wherein at least one of the first addition circuit or the first feedback circuit includes a phase compensator.
Abstract translation: ΔΣ调制器包括具有运算放大器的积分器的滤波电路; 第一加法电路，设置在滤波器电路的输出部分和量化器的输入部分之间，并包括第一电阻元件; 以及第二加法电路，其包括包括第二电阻元件或第一反馈电路的第一前馈电路中的至少一个，所述第一反馈电路被配置为将由量化器量化的数字输出信号作为模拟信号反馈到 所述量化器，其中所述第一加法电路或所述第一反馈电路中的至少一个包括相位补偿器。
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