公开(公告)号：US20240161957A1

公开(公告)日：2024-05-16

申请号：US18498128

申请日：2023-10-31

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Pao-Hung CHOU ,  Shih-Ping HSU ,  Chu-Chin HU

IPC: H01F17/00 ,  H01F27/40 ,  H01F41/04

CPC classification number: H01F17/0006 ,  H01F27/40 ,  H01F41/041 ,  H01F2017/0066 ,  H01F2017/0073 ,  H01L24/16 ,  H01L28/10 ,  H01L2224/16227

Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.

公开(公告)号：US20240096838A1

公开(公告)日：2024-03-21

申请号：US18469450

申请日：2023-09-18

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Chu-Chin HU ,  Shih-Ping HSU ,  Chih-Kuai YANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L24/29 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L2224/08235 ,  H01L2224/08238 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29084 ,  H01L2224/29139 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2957 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2924/35121

Abstract: A component-embedded packaging structure is provided, in which a plurality of metal layers are formed on an inactive surface of a semiconductor chip so as to serve as a buffer portion, and the semiconductor chip is disposed on a carrying portion with the buffer portion via an adhesive. Then, the semiconductor chip is encapsulated by an insulating layer, and a build-up circuit structure is formed on the insulating layer and electrically connected to the semiconductor chip. Therefore, the buffer portion can prevent delamination from occurring between the semiconductor chip and the adhesive on the carrying portion if the semiconductor chip has a CTE (Coefficient of Thermal Expansion) less than a CTE of the adhesive.

公开(公告)号：US20150382469A1

公开(公告)日：2015-12-31

申请号：US14492716

申请日：2014-09-22

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Chu-Chin HU ,  Shih-Ping HSU ,  E-Tung CHOU

IPC: H05K1/18 ,  H05K3/40 ,  H05K3/28 ,  H05K1/14 ,  H05K3/34

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/187 ,  H05K1/188 ,  H05K3/0014 ,  H05K3/0017 ,  H05K3/007 ,  H05K3/16 ,  H05K3/181 ,  H05K3/284 ,  H05K3/421 ,  H05K2201/0162 ,  H05K2201/0209 ,  H05K2201/09118 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09636 ,  H05K2201/09854 ,  H05K2203/025 ,  H05K2203/0369 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K2203/1316 ,  H05K2203/1461 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A package apparatus comprises a first wiring layer, a first conductive pillar layer, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface that are arranged opposite to each other. The first conductive pillar layer is disposed on the second surface of the first wiring layer, whereas the first conductive pillar layer is a non-circular conductive pillar layer. The first molding compound layer is disposed within a specific portion of the first wiring layer and the first conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the first conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.

Abstract translation: 包装装置包括第一布线层，第一导电柱层，第一模塑料层，第二布线层和保护层。 第一布线层具有彼此相对布置的第一表面和第二表面。 第一导电柱层设置在第一布线层的第二表面上，而第一导电柱层是非圆形导电柱层。 第一模塑料层设置在第一布线层和第一导电柱层的特定部分内。 第二布线层设置在第一模塑料层和第一导电柱层的一端。 保护层设置在第一模塑料层和第二布线层上。