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431 条记录 (耗时 0.019 秒)

    Method of preventing short circuits in magnetic film stacks
    1.
    发明授权
    Method of preventing short circuits in magnetic film stacks 失效
    防止磁性薄膜堆叠短路的方法

    公开(公告)号：US06893893B2

    公开(公告)日：2005-05-17

    申请号：US10235100

    申请日：2002-09-04

    申请人： Padmapani C. Nallan ,  Ajay Kumar ,  Jeng H. Hwang ,  Guangxiang Jin ,  Ralph Kerns

    发明人： Padmapani C. Nallan ,  Ajay Kumar ,  Jeng H. Hwang ,  Guangxiang Jin ,  Ralph Kerns

    IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L43/12

    CPC分类号： H01L23/564 ,  H01L21/67069 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.

    摘要翻译： 一种用于防止多层磁性膜堆叠中的电短路的方法包括提供包括具有暴露表面的磁性材料层的膜堆叠。 保护层沉积在磁性层的暴露表面上。 保护层可以包括例如碳氟化合物或氢氟烃。 蚀刻薄膜叠层并且保护层保护暴露的表面免受在蚀刻薄膜叠层时产生的导电残留物。 该方法可以用于膜堆叠中以形成磁阻随机存取存储器（MRAM）装置。

    Method for dicing a semiconductor wafer
    2.
    发明授权
    Method for dicing a semiconductor wafer 有权
    切割半导体晶片的方法

    公开(公告)号：US06642127B2

    公开(公告)日：2003-11-04

    申请号：US10035372

    申请日：2001-10-19

    申请人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

    发明人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

    IPC分类号： H01L21301

    CPC分类号： H01L21/304 ,  H01L21/78

    摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

    摘要翻译： 一种使用等离子体蚀刻工艺对半导体晶片进行切割的方法和装置。 该方法开始于将图案化掩模应用于晶片上的集成电路。 模式涵盖电路并暴露骰子之间的街道。 接下来，该方法将均匀的粘合剂材料层沉积在载体晶片上。 要切割的晶片通过夹在要切割的晶片的底表面和载体晶片的顶表面之间的粘合剂材料固定到载体晶片上。 将要切割的载体晶片，粘合剂和晶片的组合组件放置在能够蚀刻硅的蚀刻反应器中。 当将反应性气体施加到组合组件时，蚀刻等离子体将消耗街道内的未受保护的硅，并将晶片切割成单独的集成电路芯片。 然后将载体晶片从蚀刻室移除，其中骰子仍附着到粘合剂层。 使用众所周知的方法去除粘合剂材料以及任何掩模材料，并将骰子从载体晶片上分离。

    Method for plasma etching of high-K dielectric materials
    9.
    发明授权
    Method for plasma etching of high-K dielectric materials 失效
    高K电介质材料等离子体蚀刻方法

    公开(公告)号：US06902681B2

    公开(公告)日：2005-06-07

    申请号：US10184301

    申请日：2002-06-26

    申请人： Padmapani C. Nallan ,  Ajay Kumar

    发明人： Padmapani C. Nallan ,  Ajay Kumar

    IPC分类号： H01L21/28 ,  H01L21/311 ,  B44C1/22

    CPC分类号： H01L21/31122 ,  H01L21/28123

    摘要： A method of etching high dielectric constant materials (a material with a dielectric constant greater than 4) using a halogen gas, reducing gas, and passivating gas chemistry. An embodiment of the method is accomplished using chlorine, carbon monoxide, and nitrogen to etch and passivate a hafnium dioxide layer.

    摘要翻译： 使用卤素气体，还原气体和钝化气体化学法蚀刻高介电常数材料（介电常数大于4的材料）的方法。 使用氯气，一氧化碳和氮气来实现该方法的一个实施例，以蚀刻和钝化二氧化铪层。

    Method of etching a trench in a silicon-on-insulator (SOI) structure
    10.
    发明授权
    Method of etching a trench in a silicon-on-insulator (SOI) structure 失效
    蚀刻绝缘体上硅（SOI）结构中的沟槽的方法

    公开(公告)号：US06759340B2

    公开(公告)日：2004-07-06

    申请号：US10143269

    申请日：2002-05-09

    申请人： Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

    发明人： Padmapani C. Nallan ,  Ajay Kumar ,  Anisul H. Khan ,  Chan-Syun David Yang

    IPC分类号： H01L21302

    CPC分类号： H01L21/30655

    摘要： Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

    摘要翻译： 本文公开了一种在覆盖电介质材料的硅中蚀刻沟槽的方法，其减小或基本上消除在沟槽的基部处的凹口，同时减少沟槽侧壁上的扇形。 该方法包括通过将硅衬底通过图案化掩模层暴露于由含氟气体产生的等离子体来蚀刻沟槽的第一部分。 该蚀刻之后是聚合物沉积步骤，包括将衬底暴露于由能够在蚀刻的硅表面上形成聚合物的气体产生的等离子体。 根据沟槽第一部分的期望深度，蚀刻和聚合物沉积步骤重复多个循环。 通过将硅暴露于由含氟气体和聚合物形成气体的组合产生的等离子体来蚀刻沟槽的最后部分。