公开(公告)号：US5789320A

公开(公告)日：1998-08-04

申请号：US636456

申请日：1996-04-23

申请人： Panayotis Constantinou Andricacos ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger ,  Alejandro Gabriel Schrott

发明人： Panayotis Constantinou Andricacos ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger ,  Alejandro Gabriel Schrott

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/44

CPC分类号： H01L27/1085 ,  H01L28/60

摘要： Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.

摘要翻译： 用于DRAM和FRAM的电极的制造中使用预先存在的种子层上的贵金属电镀。 电镀可以是空间选择性的或非选择性的。 在非选择性情况下，首先将覆盖膜镀覆，然后通过空间选择性材料去除在沉积后进行图案化。 在选择性情况下，电镀沉积物可以通过通孔掩模技术在光刻定义的区域中选择性地生长，或者在预先存在的电极结构的暴露区域上选择性地生长为保形涂层。 在电镀工艺中可以使用类金刚石碳膜。 公开了一种自对准工艺，用于在通过掩模工艺中选择性地涂覆绝缘体。

公开(公告)号：US5757612A

公开(公告)日：1998-05-26

申请号：US636624

申请日：1996-04-23

申请人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

发明人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01G4/06

CPC分类号： H01L27/10852 ,  H01L28/55

摘要： Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

摘要翻译： 用于存储器单元应用的结构，包括用于DRAM的电容器和来自FRAM的铁电存储器单元，其制造方法包括沉积铁电体或高ε电介质材料以完全填充空腔，其几何宽度是电学厚度的唯一决定因素 最终装置中铁电或高ε电介质层的有效部分。 在优选实施例中，沉积电介质的空腔由在电介质沉积之前的通过掩模镀层步骤中沉积和图案化的板和堆叠电极之间的间隙限定。

公开(公告)号：US06242321B1

公开(公告)日：2001-06-05

申请号：US09303595

申请日：1999-05-03

申请人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

发明人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

IPC分类号： H01L2176

CPC分类号： H01L27/10852 ,  H01L28/55

摘要： Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

摘要翻译： 用于存储器单元应用的结构，包括用于DRAM的电容器和来自FRAM的铁电存储器单元，其制造方法包括沉积铁电体或高ε电介质材料以完全填充空腔，其几何宽度是电学厚度的唯一决定因素 最终装置中铁电或高ε电介质层的有效部分。 在优选实施例中，沉积电介质的空腔由在电介质沉积之前的通过掩模镀层步骤中沉积和图案化的板和堆叠电极之间的间隙限定。

公开(公告)号：US06391773B2

公开(公告)日：2002-05-21

申请号：US09733188

申请日：2000-12-09

申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

IPC分类号： H01L2144

CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

公开(公告)号：US06188120B1

公开(公告)日：2001-02-13

申请号：US08805403

申请日：1997-02-24

申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

IPC分类号： H01L27108

CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

公开(公告)号：US6030904A

公开(公告)日：2000-02-29

申请号：US916001

申请日：1997-08-21

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/477

CPC分类号： H01L21/312 ,  H01L21/31058 ,  H01L21/76807

摘要： A method for treating a film of carbon-based dielectric material such as diamond-like carbon to remove volatiles is described. The method incorporates the steps of providing a non-oxidizing ambient and heating the film above 350.degree. C. Heating may be by rapid thermal annealing. The dielectric constant of the material may be lowered. A stabilized carbon-based material is provided with less than 0.5% thickness or weight change/hour at a selected temperature at or below 400.degree. C. The invention overcomes the problem of dimensional instability during the incorporation of the material in integrated circuit chips as an intra and inter level dielectric.

摘要翻译： 描述了一种用于处理诸如类金刚石碳的碳基电介质材料膜以除去挥发物的方法。 该方法包括提供非氧化环境并将膜加热到350℃以上的步骤。加热可以通过快速热退火。 材料的介电常数可能会降低。 在等于或低于400℃的选定温度下，稳定的碳基材料提供小于0.5％的厚度或重量变化/小时。本发明克服了在将材料掺入集成电路芯片中时的尺寸不稳定性的问题，作为 内部和中间电介质。

公开(公告)号：US06448655B1

公开(公告)日：2002-09-10

申请号：US09067439

申请日：1998-04-28

申请人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L2348

CPC分类号： H01L21/76825 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.

摘要翻译： 描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。 本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

公开(公告)号：US06448176B1

公开(公告)日：2002-09-10

申请号：US09699900

申请日：2000-10-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

摘要翻译： 本发明涉及用于在衬底中形成双浮雕图案的平版印刷方法，以及通过双镶嵌工艺制造半导体芯片中的多层互连结构的方法，其中形成在电介质中的双浮雕空穴填充有导电材料 形成布线和通孔层。 本发明包括通过添加易于整合的侧壁衬里而修改的两次图案化单掩膜层双镶嵌工艺，以保护有机层间和层间电介质免受光刻胶剥离步骤在光刻返工期间引起的潜在损伤。 本发明还包括一种用于形成双重图案硬掩模的方法，该双面图案硬掩模可用于形成用于双镶嵌处理​​的双浮雕空腔，所述双图案硬掩模包括具有第一图案的一层或多层第一组和 具有第二图案的第二组一层或多层。

公开(公告)号：US06265779B1

公开(公告)日：2001-07-24

申请号：US09132608

申请日：1998-08-11

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21283

CPC分类号： H01L21/0212 ,  H01L21/02115 ,  H01L21/02131 ,  H01L21/3127 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Metal and insulator interconnect structures are described incorporating one or more layers of fluorinated dielectric insulation, one or more conductive wiring levels interconnected by vias and capping and/or liner materials to physically isolate the wiring levels and vias from the fluorinated dielectric such as fluorinated diamond like carbon which has a low dielectric constant. The invention overcomes the problem that can arise when fluorine in the fluorinated dielectric insulation reacts with other materials in the interconnect structure to produce unwanted fluorine-containing compounds that can interfere with the structure's mechanical integrity or interconnect function.

摘要翻译： 描述了金属和绝缘体互连结构，其包括一层或多层氟化电介质绝缘体，通过通孔和封盖和/或衬垫材料互连的一个或多个导电布线层，以物理地隔离氟化电介质的布线层和通孔，例如氟化金刚石 具有低介电常数的碳。 本发明克服了当氟化绝缘绝缘体中的氟与互连结构中的其它材料反应产生不想要的含氟化合物时可能出现的问题，这些化合物可能会干扰结构的机械完整性或互连功能。

公开(公告)号：US06759321B2

公开(公告)日：2004-07-06

申请号：US10205526

申请日：2002-07-25

申请人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76825 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.

摘要翻译： 描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。 本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。