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    Structure and fabrication method for non-planar memory elements
    3.
    发明授权
    Structure and fabrication method for non-planar memory elements 失效
    非平面记忆元件的结构和制造方法

    公开(公告)号：US06242321B1

    公开(公告)日：2001-06-05

    申请号：US09303595

    申请日：1999-05-03

    申请人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

    发明人： Raul Edmundo Acosta ,  James Hartfiel Comfort ,  Alfred Grill ,  David Edward Kotecki ,  Katherine Lynn Saenger

    IPC分类号： H01L2176

    CPC分类号： H01L27/10852 ,  H01L28/55

    摘要： Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

    摘要翻译： 用于存储器单元应用的结构，包括用于DRAM的电容器和来自FRAM的铁电存储器单元，其制造方法包括沉积铁电体或高ε电介质材料以完全填充空腔，其几何宽度是电学厚度的唯一决定因素 最终装置中铁电或高ε电介质层的有效部分。 在优选实施例中，沉积电介质的空腔由在电介质沉积之前的通过掩模镀层步骤中沉积和图案化的板和堆叠电极之间的间隙限定。

    Compound electrode stack capacitor
    4.
    发明授权
    Compound electrode stack capacitor 失效
    复合电极堆叠电容器

    公开(公告)号：US5825609A

    公开(公告)日：1998-10-20

    申请号：US636457

    申请日：1996-04-23

    申请人： Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01G4/06

    CPC分类号： H01L28/82 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/1085 ,  H01L28/91 ,  H01L28/55

    摘要： This invention is directed to a semiconductor memory device including a storage element having a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

    摘要翻译： 本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间具有铁电材料或电容器电介质材料的存储元件。 特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化 其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。 相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

    Compound electrode stack capacitor
    5.
    发明授权
    Compound electrode stack capacitor 失效
    复合电极堆叠电容器

    公开(公告)号：US5998250A

    公开(公告)日：1999-12-07

    申请号：US62031

    申请日：1998-04-17

    申请人： Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  David Edward Kotecki ,  Katherine Lynn Saenger

    IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L28/82 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/1085 ,  H01L28/91 ,  H01L28/55

    摘要： This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

    摘要翻译： 本发明涉及一种半导体存储器件，其包括在顶部（板）电极和底部（堆叠）电极之间包括铁电材料或电容器电介质材料的存储元件。 特别地，本发明涉及堆叠电极的设计和制造，其被描述为化合物，因为它由两种或更多种材料组成，这两种或多种材料是单独图案化的（至少一种材料在沉积之前沉积和图案化 其他），或者被布置成使得每个组分材料显着地有助于初始沉积铁电体或电容器电介质的区域。 相对于相同尺寸的固体单材料电极，这些复合堆叠电极可以提供易于处理，更经济地使用贵金属材料以及潜在的增加的机械稳定性（例如抵抗小丘）。

    Method and materials for through-mask electroplating and selective base removal
    6.
    发明授权
    Method and materials for through-mask electroplating and selective base removal 失效
    用于通孔电镀和选择性基底去除的方法和材料

    公开(公告)号：US06391773B2

    公开(公告)日：2002-05-21

    申请号：US09733188

    申请日：2000-12-09

    申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    IPC分类号： H01L2144

    CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

    摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

    摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

    Method and materials for through-mask electroplating and selective base removal
    7.
    发明授权
    Method and materials for through-mask electroplating and selective base removal 失效
    用于通孔电镀和选择性基底去除的方法和材料

    公开(公告)号：US06188120B1

    公开(公告)日：2001-02-13

    申请号：US08805403

    申请日：1997-02-24

    申请人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    发明人： Panayotis Constantinou Andricacos ,  Cyril Cabral, Jr. ,  Roy Carruthers ,  Alfred Grill ,  Katherine Lynn Saenger

    IPC分类号： H01L27108

    CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L28/75

    摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.

    摘要翻译： 选择多层金属材料，使得材料将在快速热退火条件下合金或混合。 优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。 对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。 此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。 合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。 类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

    Stabilization of low-k carbon-based dielectrics
    8.
    发明授权
    Stabilization of low-k carbon-based dielectrics 失效
    低k碳基电介质的稳定化

    公开(公告)号：US6030904A

    公开(公告)日：2000-02-29

    申请号：US916001

    申请日：1997-08-21

    申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

    发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

    IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/477

    CPC分类号： H01L21/312 ,  H01L21/31058 ,  H01L21/76807

    摘要： A method for treating a film of carbon-based dielectric material such as diamond-like carbon to remove volatiles is described. The method incorporates the steps of providing a non-oxidizing ambient and heating the film above 350.degree. C. Heating may be by rapid thermal annealing. The dielectric constant of the material may be lowered. A stabilized carbon-based material is provided with less than 0.5% thickness or weight change/hour at a selected temperature at or below 400.degree. C. The invention overcomes the problem of dimensional instability during the incorporation of the material in integrated circuit chips as an intra and inter level dielectric.

    摘要翻译： 描述了一种用于处理诸如类金刚石碳的碳基电介质材料膜以除去挥发物的方法。 该方法包括提供非氧化环境并将膜加热到350℃以上的步骤。加热可以通过快速热退火。 材料的介电常数可能会降低。 在等于或低于400℃的选定温度下，稳定的碳基材料提供小于0.5％的厚度或重量变化/小时。本发明克服了在将材料掺入集成电路芯片中时的尺寸不稳定性的问题，作为 内部和中间电介质。

    Dual damascene processing for semiconductor chip interconnects
    10.
    发明授权
    Dual damascene processing for semiconductor chip interconnects 有权
    用于半导体芯片互连的双镶嵌处理

    公开(公告)号：US06448176B1

    公开(公告)日：2002-09-10

    申请号：US09699900

    申请日：2000-10-30

    申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

    发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

    IPC分类号： H01L214763

    CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

    摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

    摘要翻译： 本发明涉及用于在衬底中形成双浮雕图案的平版印刷方法，以及通过双镶嵌工艺制造半导体芯片中的多层互连结构的方法，其中形成在电介质中的双浮雕空穴填充有导电材料 形成布线和通孔层。 本发明包括通过添加易于整合的侧壁衬里而修改的两次图案化单掩膜层双镶嵌工艺，以保护有机层间和层间电介质免受光刻胶剥离步骤在光刻返工期间引起的潜在损伤。 本发明还包括一种用于形成双重图案硬掩模的方法，该双面图案硬掩模可用于形成用于双镶嵌处理​​的双浮雕空腔，所述双图案硬掩模包括具有第一图案的一层或多层第一组和 具有第二图案的第二组一层或多层。