利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.027 秒)

    Methods for fabricating deep trench capacitors
    1.
    发明授权
    Methods for fabricating deep trench capacitors 有权
    制造深沟槽电容器的方法

    公开(公告)号：US08609486B1

    公开(公告)日：2013-12-17

    申请号：US13345630

    申请日：2012-01-06

    申请人： Peter Smeys ,  Charu Sardana

    发明人： Peter Smeys ,  Charu Sardana

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L29/945

    摘要： Integrated circuits with transistors and decoupling capacitor structures are provided. A decoupling capacitor structure may include multiple deep trench structures formed in a semiconductor substrate. The deep trench structures may each be lined with high-κ dielectric material. A conductive metal layer for use in controlling threshold voltages associated with n-channel or p-channel devices may be formed over the high-κ dielectric liner. Conductive material such as aluminum may be used to fill the remaining trench cavity. The high-κ dielectric liner may be simultaneously deposited into the deep trench structures and gate regions of the transistors. In one suitable arrangement, the deep trench structures and transistor metal gates for at least a selected type of transistors may be formed in parallel. In another suitable arrangement, the deep trench structures and the transistor metal gates may be formed in separate steps.

    摘要翻译： 提供了具有晶体管和去耦电容器结构的集成电路。 去耦电容器结构可以包括形成在半导体衬底中的多个深沟槽结构。 深沟槽结构可以各自用高kappa介电材料衬里。 用于控制与n沟道或p沟道器件相关联的阈值电压的导电金属层可以形成在高卡介质衬垫上。 可以使用诸如铝的导电材料来填充剩余的沟槽空腔。 高卡介质衬垫可以同时沉积到晶体管的深沟槽结构和栅极区域中。 在一种合适的布置中，用于至少一种选定类型的晶体管的深沟槽结构和晶体管金属栅极可以并联形成。 在另一种合适的布置中，深沟槽结构和晶体管金属栅极可以分开形成。

    Methods of forming inductors on integrated circuits
    5.
    发明授权
    Methods of forming inductors on integrated circuits 有权
    在集成电路上形成电感器的方法

    公开(公告)号：US08042260B2

    公开(公告)日：2011-10-25

    申请号：US12250385

    申请日：2008-10-13

    申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  Andrei Papou

    IPC分类号： H01F7/06

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

    摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.

    摘要翻译： 所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。 在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。 第一组间隔开的金属芯元件形成在衬底上。 然后在芯元件的侧表面上形成隔离侧壁。 之后，在衬底上形成第二组金属芯元件。 第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。 具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE
    7.
    发明申请
    CMOS COMPATIBLE INTEGRATED HIGH DENSITY CAPACITOR STRUCTURE AND PROCESS SEQUENCE 审中-公开
    CMOS兼容一体化高密度电容器结构和工艺顺序

    公开(公告)号：US20100079929A1

    公开(公告)日：2010-04-01

    申请号：US12243123

    申请日：2008-10-01

    申请人： Peter Smeys ,  Peter Johnson

    发明人： Peter Smeys ,  Peter Johnson

    IPC分类号： H01G9/07 ,  H01G9/00

    CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01L21/02183 ,  H01L21/02258 ,  H01L21/31687 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

    摘要： Integrated circuits structures and process sequences are provided for forming CMOS compatible high-density capacitors. The anodization of tantalum to tantalum oxide in the formation of the inter-plate capacitor dielectric results in very high dielectric constants since the defects usually found in the inter-plate dielectric are eliminated in the volume expansion that occurs during the oxidation of the tantalum material. This permits the fabrication of larger capacitors that can be incorporated into standard CMOS process flows.

    摘要翻译： 集成电路结构和工艺顺序被提供用于形成CMOS兼容的高密度电容器。 在形成板间电容器电介质中，钽到氧化钽的阳极氧化导致非常高的介电常数，因为在钽材料的氧化期间发生的体积膨胀中消除了在板间电介质中通常发现的缺陷。 这允许制造可并入标准CMOS工艺流程的较大电容器。