公开(公告)号：US20240145155A1

公开(公告)日：2024-05-02

申请号：US18499111

申请日：2023-10-31

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Pao-Hung CHOU ,  Che-Wei HSU ,  Shih-Ping HSU

IPC: H01F27/26 ,  H01F41/18 ,  H01F41/26

CPC classification number: H01F27/263 ,  H01F41/18 ,  H01F41/26 ,  H01L28/10

Abstract: Provided is a core structure of an inductor element. The manufacturing method thereof is to embed a magnetic conductor including at least one magnetic conductive layer in a core body and to from a plurality of apertures for passing coils around the magnetic conductor in the core body. Accordingly, the magnetic conductor is designed in the core body by using the integrated circuit carrier board manufacturing process, such that the overall size and thickness of the inductor element can be greatly reduced, thereby facilitating product miniaturization using the inductor element.

公开(公告)号：US20240221999A1

公开(公告)日：2024-07-04

申请号：US18481059

申请日：2023-10-04

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Che-Wei HSU ,  Pao-Hung CHOU

IPC: H01F27/32 ,  H01F41/04 ,  H01F41/12

CPC classification number: H01F27/323 ,  H01F41/041 ,  H01F41/122

Abstract: An inductor structure is provided, in which a coil-shaped inductor body and a magnetically permeable alloy layer located in the coil are embedded in an insulator, so as to improve the electrical characteristics of the inductor via the design of the magnetically permeable alloy layer. Therefore, the inductor structure of the present disclosure can meet the required requirements without using a mixture of conventional magnetically permeable elements and conventional magnetic powders.

公开(公告)号：US20180255651A1

公开(公告)日：2018-09-06

申请号：US15973522

申请日：2018-05-07

Applicant: Phoenix Pioneer technology Co.,Ltd.

Inventor： Che-Wei HSU ,  Shih-Ping HSU ,  Pao-Hung CHOU

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L23/12 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H05K3/4647 ,  Y10T29/49165

Abstract: A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.

公开(公告)号：US20160073516A1

公开(公告)日：2016-03-10

申请号：US14541688

申请日：2014-11-14

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Pao-Hung CHOU ,  Shih-Ping HSU ,  Che-Wei HSU

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of fabricating an interposer substrate is provided, including: providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer; forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer; forming a second wiring layer on the first insulating layer and the conductive pillars; disposing a plurality of external connection pillars on the second wiring layer; forming a second insulating layer on the first insulating layer, with the external connection pillars being exposed from the second insulating layer; forming at least a trench on the second insulating layer; and removing the carrier. Through the formation of the interposer substrate, which does not have a core layer, on the carrier, a via process is omitted. Therefore, the method is simple, and the interposer substrate thus fabricated has a low cost. The present invention further provides the interposer substrate.

Abstract translation: 提供一种制造插入器基板的方法，包括：提供具有第一布线层和布置在第一布线层上的多个导电柱的载体; 在载体上形成第一绝缘层，导电柱从第一绝缘层露出; 在所述第一绝缘层和所述导电柱上形成第二布线层; 在所述第二布线层上设置多个外部连接柱; 在所述第一绝缘层上形成第二绝缘层，所述外部连接柱从所述第二绝缘层露出; 在所述第二绝缘层上形成至少沟槽; 并移除载体。 通过在载体上形成不具有芯层的插入基板，省略了通孔工艺。 因此，该方法简单，并且由此制造的内插基板具有低成本。 本发明还提供了内插基板。

公开(公告)号：US20240222140A1

公开(公告)日：2024-07-04

申请号：US18393823

申请日：2023-12-22

Applicant: Phoenix Pioneer Technology Co., Ltd.

Inventor： Che-Wei HSU ,  Pao-Hung CHOU ,  Shih-Ping HSU

IPC: H01L21/48 ,  H01L21/283 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L21/4857 ,  H01L21/283 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2224/73103 ,  H01L2924/18162

Abstract: A package carrier board includes a first circuit build-up structure, a patterned magnetic conductive metal layer, a plurality of first conductive pillar, a second insulating layer, and a second circuit build-up structure. The patterned magnetic conductive metal layer is disposed above the first circuit build-up structure, and the cross-sectional pattern of the patterned magnetic conductive metal layer is L-shaped and/or U-shaped. The first conductive pillars are disposed on the first circuit build-up structure and located outside of the patterned magnetic conductive metal layer. The second insulating layer covers the patterned magnetic conductive metal layer and the first conductive pillars. The second circuit build-up structure is disposed on the second insulating layer. The first circuit build-up structure, the first conductive pillars, the second insulating layer, and the second circuit build-up structure are combined to form an inductive circuit structure. Additionally, a manufacturing method for the package carrier board is also disclosed.

公开(公告)号：US20250142728A1

公开(公告)日：2025-05-01

申请号：US18927787

申请日：2024-10-25

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Che-Wei HSU ,  Wen-Hung HU ,  Shih-Ping HSU

IPC: H05K1/16 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46

Abstract: Provided is a coil carrier board, including a base coil layer, a conductive layer stacked on and bonded to the base coil layer, at least one build-up coil layer stacked on and bonded to the conductive layer, and an opening connecting the base coil layer, the conductive layer and the build-up coil layer. The coil carrier board has thick copper, fine line spacing and appropriate rigidity by means of the build-up circuit process and the structural design of the insulating layer of a photosensitive dielectric material bonded with a thermosetting dielectric material. Accordingly, the high current-carrying efficiency of the coil carrier board is enhanced, and the overall structure of the coil carrier board has better flatness, rigidity and high interlayer alignment accuracy, thereby facilitating miniaturization and automated assembly production.

公开(公告)号：US20230187402A1

公开(公告)日：2023-06-15

申请号：US18072694

申请日：2022-11-30

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Wen-Chang CHEN ,  Che-Wei HSU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L23/3107 ,  H01L21/56 ,  H01L2224/24011

Abstract: An electronic package is provided, in which a surface treatment layer is formed on parts of a surface of a functional pad, such that an electronic element is in contact with and bonded to the functional pad and the surface treatment layer via a bonding layer. Therefore, when the electronic package undergoes thermal shock, the surface treatment layer having buffering capability can improve packaging reliability of the electronic package.

公开(公告)号：US20160064317A1

公开(公告)日：2016-03-03

申请号：US14547743

申请日：2014-11-19

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Che-Wei HSU ,  Shih-Ping HSU ,  Chih-Wen LIU

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/13 ,  H01L23/145 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/0152 ,  H01L2924/00

Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

Abstract translation: 一种制造插入器基板的方法，包括提供其上形成有第一电路层的载体，在第一电路层上形成多个导电柱，在载体上形成第一绝缘层，导电柱从第一 绝缘层，在所述导电柱上形成电连接到所述导电柱的第二电路层，在所述第一绝缘层和所述第二电路层的所述第二表面上形成第二绝缘层，暴露所述第二绝缘层的第二表面的一部分 电路层，并且移除载体。 本发明还提供如上所述的插入器基板。