公开(公告)号：US20180047660A1

公开(公告)日：2018-02-15

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L24/02 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/10719

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

公开(公告)号：US20170372975A1

公开(公告)日：2017-12-28

申请号：US15191062

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H01L21/66 ,  H01L23/544 ,  H01L23/66

CPC classification number: H01L22/32 ,  H01L23/544 ,  H01L27/13 ,  H01L2223/5446 ,  H01L2223/54493 ,  H03H7/00 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0078 ,  H04B1/0057

Abstract: A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric layer supported by the die. The RF integrated circuit may also include an inline pad structure coupled to the at least one pair of capacitors proximate an edge of the die. The inline pad structure may include a first portion and a second portion extending into a dicing street toward the edge of the die and covered by at least a second dielectric layer.

公开(公告)号：US20170338788A1

公开(公告)日：2017-11-23

申请号：US15161138

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H03H7/01 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H03H1/00 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K1/16

CPC classification number: H03H7/1758 ,  H01F5/003 ,  H01F41/04 ,  H01F41/041 ,  H01P1/203 ,  H01P1/2135 ,  H01P5/12 ,  H03H1/00 ,  H03H7/0115 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/463 ,  H03H2001/0078 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/18 ,  H05K3/4038

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

公开(公告)号：US20170200550A1

公开(公告)日：2017-07-13

申请号：US14991803

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM

IPC: H01F27/28 ,  H04B1/40 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5222 ,  H01L23/5227 ,  H01L27/0207 ,  H01L28/10 ,  H04B1/40

Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.

公开(公告)号：US20170125512A1

公开(公告)日：2017-05-04

申请号：US15375137

申请日：2016-12-11

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Donald William KIDWELL JR ,  Jon Bradley LASITER ,  Kwan-Yu LAI ,  Jitae KIM ,  Ravindra Vaman SHENOY

IPC: H01L49/02

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

公开(公告)号：US20160020013A1

公开(公告)日：2016-01-21

申请号：US14335609

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01F27/28 ,  H01F41/04 ,  H01F27/29

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

公开(公告)号：US20150228712A1

公开(公告)日：2015-08-13

申请号：US14177072

申请日：2014-02-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Donald William KIDWELL ,  Jon Bradley LASITER ,  Kwan-Yu LAI ,  Jitae KIM ,  Ravindra Vaman SHENOY

IPC: H01L49/02 ,  H01L23/48

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：US20190035621A1

公开(公告)日：2019-01-31

申请号：US15659591

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU

IPC: H01L21/02 ,  H01L21/67 ,  H01L23/15 ,  H01L21/20

Abstract: To overcome the deficiencies of conventional rectangular circuit wafers, a glass substrate circuit wafer with an obtuse angle on the perimeter may be used. In one example, a glass substrate wafer may include a first circuit on a first portion of a glass substrate and a second circuit on a second portion of the glass substrate where the first portion has a first obtuse angle and the second portion has a second obtuse angle that is complementary to the first obtuse angle on the perimeter of the first portion to mate together to form an outer perimeter that comprises right angles.

公开(公告)号：US20180054177A1

公开(公告)日：2018-02-22

申请号：US15240987

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Changhan Hobie YUN ,  Chengjie ZUO ,  Shiqun GU ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H03H7/01 ,  H03H1/00 ,  H03H7/46 ,  H01L49/02

CPC classification number: H03H7/0115 ,  H01L28/10 ,  H01L28/40 ,  H03H1/0007 ,  H03H7/0138 ,  H03H7/46 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09263 ,  H05K2201/09281

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：US20180047687A1

公开(公告)日：2018-02-15

申请号：US15233902

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jie FU ,  Manuel ALDRETE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Mario Francisco VELEZ

IPC: H01L23/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15321 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device according to some examples of the disclosure may include a package substrate, a semiconductor die coupled to one side of the package substrate with a first set of contacts on an active side of the semiconductor die and coupled to a plurality of solder prints with a second set of contacts on a back side of the semiconductor die. The semiconductor die may include a plurality of vias connecting the first set of contacts to the second set of contacts and configured to allow heat to be transferred from the active side of the die to the plurality of solder prints for a shorter heat dissipation path.