公开(公告)号：US06509622B1

公开(公告)日：2003-01-21

申请号：US09644639

申请日：2000-08-23

申请人： Qing Ma ,  Jin Lee ,  Quan Tran ,  Harry Fujimoto

发明人： Qing Ma ,  Jin Lee ,  Quan Tran ,  Harry Fujimoto

IPC分类号： H01L27095

CPC分类号： H01L23/585 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit including a die having a circuit area and a plurality of guard rings. The circuit area includes active devices, passive devices, and interconnects connected to form an integrated circuit. The plurality of guard rings includes a plurality of stacked guard rings having substantially equal widths and encircling the circuit area. Alternatively, the plurality of guard rings includes metallization level guard rings interleaved with one or more via level guard rings. Each of the one or more via level guard rings includes one or more guard rings encircling the circuit area. Alternatively, the plurality of guard rings includes a plurality of concentric guard rings encircling the circuit area. Each of the plurality of guard rings is fabricated from a metal, such as aluminum, copper, or silver, or an alloy of aluminum, copper, or silver.

摘要翻译： 一种集成电路，包括具有电路区域和多个保护环的管芯。 电路区域包括有源器件，无源器件和互连，形成集成电路。 多个保护环包括多个具有基本上相等的宽度并且围绕电路区域的堆叠保护环。 或者，多个保护环包括与一个或多个通孔级保护环交错的金属化水平保护环。 一个或多个通孔级保护环中的每一个包括环绕电路区域的一个或多个保护环。 或者，多个保护环包括环绕电路区域的多个同心保护环。 多个保护环中的每一个由诸如铝，铜或银的金属或铝，铜或银的合金制成。

公开(公告)号：US07411269B2

公开(公告)日：2008-08-12

申请号：US11091967

申请日：2005-03-28

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/72

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

公开(公告)号：US06876053B1

公开(公告)日：2005-04-05

申请号：US09374502

申请日：1999-08-13

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L21/762 ,  H01L29/00 ,  H01L29/76 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US20070013023A1

公开(公告)日：2007-01-18

申请号：US11525982

申请日：2006-09-22

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/00

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US07410858B2

公开(公告)日：2008-08-12

申请号：US11437379

申请日：2006-05-19

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/72

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US20060220147A1

公开(公告)日：2006-10-05

申请号：US11437379

申请日：2006-05-19

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US20050179109A1

公开(公告)日：2005-08-18

申请号：US11091967

申请日：2005-03-28

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L21/762 ,  H01L29/00 ,  H01L29/76 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

公开(公告)号：US06219243B1

公开(公告)日：2001-04-17

申请号：US09461469

申请日：1999-12-14

申请人： Qing Ma ,  Lise Varner ,  Harry Fujimoto

发明人： Qing Ma ,  Lise Varner ,  Harry Fujimoto

IPC分类号： H05K720

CPC分类号： H05K1/0204 ,  H01L23/36 ,  H01L23/3677 ,  H01L2224/32225 ,  H01L2924/15311 ,  H05K2201/09054 ,  H05K2201/10734

摘要： An enhanced heat dissipation device for a chip-on-flex packaged unit includes a flex circuit material attached to a front side of an integrated circuit die. The flex circuit material further attached to a bottom side of a printed circuit board having an opening to expose the flex circuit material. A top heat spreader thermally coupled to the flex circuit material through the opening in the printed circuit to dissipate heat from the front side of the integrated circuit die. The device further includes a bottom heat spreader, that is thermally coupled to back side of the integrated circuit die, to dissipate heat from the back side of the integrated circuit die. This enables the heat dissipation device to dissipate heat from both the front side and back side of the integrated circuit die, and thereby enhancing the heat dissipation for a given unit surface are of the integrated circuit die without increasing the volume of the heat dissipation device.

摘要翻译： 用于芯片上的柔性封装单元的增强的散热装置包括附接到集成电路管芯的前侧的柔性电路材料。 柔性电路材料进一步附接到具有开口的印刷电路板的底侧以暴露柔性电路材料。 顶部散热器，其通过印刷电路中的开口热耦合到柔性电路材料，以从集成电路管芯的前侧消散热量。 该装置还包括热耦合到集成电路管芯的背侧的底部散热器，以从集成电路管芯的背面散发热量。 这使得散热装置能够从集成电路管芯的前侧和后侧散发热量，从而增加给定单元表面的散热是集成电路管芯而不增加散热装置的体积。

公开(公告)号：US06562653B1

公开(公告)日：2003-05-13

申请号：US09668770

申请日：2000-09-22

申请人： Qing Ma ,  Harry Fujimoto

发明人： Qing Ma ,  Harry Fujimoto

IPC分类号： H01L2150

CPC分类号： H01L23/49827 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2924/3011

摘要： An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon subtstrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

摘要翻译： 一种集成电路封装，其包括连接到硅衬底的集成电路。 硅衬底可以具有通孔。 该封装还可以包括连接到集成电路和硅基板两者的焊料凸块。 硅衬底具有与集成电路的热膨胀系数相匹配的热膨胀系数。

公开(公告)号：US06271469B1

公开(公告)日：2001-08-07

申请号：US09438221

申请日：1999-11-12

申请人： Qing Ma ,  Chun Mu ,  Harry Fujimoto

发明人： Qing Ma ,  Chun Mu ,  Harry Fujimoto

IPC分类号： H01L2302

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/485 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends vertically adjacent the microelectronic die active surface and vertically adjacent the encapsulation material surface.

摘要翻译： 一种微电子封装，其包括具有活性表面和至少一个侧面的微电子管芯。 封装材料邻近微电子管芯侧设置，其中封装材料包括至少一个与微电子管芯有效表面平面的表面。 第一介电材料层可以设置在微电子管芯有源表面和封装材料表面的至少一部分上。 然后至少一个导电迹线设置在第一介电材料层上。 导电迹线与微电子管芯有源表面电接触。 至少一个导电迹线垂直邻近微电子管芯有源表面并垂直邻近封装材料表面延伸。