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公开(公告)号:US10395967B2
公开(公告)日:2019-08-27
申请号:US15628537
申请日:2017-06-20
Applicant: Renesas Electronics Corporation
Inventor: Takamitsu Yoshihara , Takahiro Kainuma , Hiroi Oka
IPC: H01L21/68 , H01L21/683 , H01L21/304 , H01L21/78 , H01L23/00 , H01L23/495
Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
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公开(公告)号:US10262927B2
公开(公告)日:2019-04-16
申请号:US15558977
申请日:2015-07-23
Applicant: Renesas Electronics Corporation
Inventor: Kazunori Hasegawa , Hiroi Oka
IPC: H01L23/00 , H01L23/495 , H01L21/52 , H01L21/48 , H01L23/31
Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).
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公开(公告)号:US09716027B2
公开(公告)日:2017-07-25
申请号:US15007275
申请日:2016-01-27
Applicant: Renesas Electronics Corporation
Inventor: Takamitsu Yoshihara , Takahiro Kainuma , Hiroi Oka
IPC: H01L21/68 , H01L21/683 , H01L21/304 , H01L21/78 , H01L23/00 , H01L23/495
CPC classification number: H01L21/6836 , H01L21/304 , H01L21/3043 , H01L21/78 , H01L23/49524 , H01L23/49562 , H01L23/49582 , H01L24/34 , H01L24/37 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2224/37147 , H01L2224/37599 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014
Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
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公开(公告)号:US10388597B2
公开(公告)日:2019-08-20
申请号:US15985957
申请日:2018-05-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Masatoshi Sugiura , Hiroi Oka
IPC: H01L23/495 , H01L23/00 , H01L21/48
Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.
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公开(公告)号:US10347567B2
公开(公告)日:2019-07-09
申请号:US16020353
申请日:2018-06-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Atsushi Nishikizawa , Yuichi Yato , Hiroi Oka , Tadatoshi Danno , Hiroyuki Nakamura
IPC: H01L23/495 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31
Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
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公开(公告)号:US09922905B2
公开(公告)日:2018-03-20
申请号:US15444773
申请日:2017-02-28
Applicant: Renesas Electronics Corporation
Inventor: Yuichi Yato , Hiroi Oka , Noriko Okunishi , Keita Takada
IPC: H01L23/00 , H01L23/495 , H01L23/13 , H01L23/31 , H01L23/24
CPC classification number: H01L23/49513 , H01L21/565 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/3121 , H01L23/3142 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49582 , H01L23/49805 , H01L23/49844 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/743 , H01L24/77 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/37147 , H01L2224/40091 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48624 , H01L2224/48644 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/743 , H01L2224/83192 , H01L2224/83439 , H01L2224/8385 , H01L2224/83862 , H01L2224/84205 , H01L2224/84439 , H01L2224/8501 , H01L2224/85181 , H01L2224/85205 , H01L2224/85439 , H01L2224/92157 , H01L2224/92247 , H01L2924/00014 , H01L2924/1301 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2924/00 , H01L2924/0665 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.
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公开(公告)号:US10037932B2
公开(公告)日:2018-07-31
申请号:US15515297
申请日:2015-03-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Atsushi Nishikizawa , Yuichi Yato , Hiroi Oka , Tadatoshi Danno , Hiroyuki Nakamura
IPC: H01L23/48 , H01L23/495 , H01L23/31 , H01L21/48 , H01L21/56
CPC classification number: H01L23/49513 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/4952 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/06 , H01L2224/05554 , H01L2224/32245 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/181 , H01L2924/00012 , H01L2924/00
Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
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公开(公告)号:US09607940B2
公开(公告)日:2017-03-28
申请号:US14901424
申请日:2013-07-05
Applicant: Renesas Electronics Corporation
Inventor: Yuichi Yato , Hiroi Oka , Noriko Okunishi , Keita Takada
IPC: H01L23/00 , H01L23/498 , H01L23/13 , H01L23/31
CPC classification number: H01L23/49513 , H01L21/565 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/3121 , H01L23/3142 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49582 , H01L23/49805 , H01L23/49844 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/743 , H01L24/77 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/37147 , H01L2224/40091 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48624 , H01L2224/48644 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/743 , H01L2224/83192 , H01L2224/83439 , H01L2224/8385 , H01L2224/83862 , H01L2224/84205 , H01L2224/84439 , H01L2224/8501 , H01L2224/85181 , H01L2224/85205 , H01L2224/85439 , H01L2224/92157 , H01L2224/92247 , H01L2924/00014 , H01L2924/1301 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2924/00 , H01L2924/0665 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.
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