公开(公告)号：US20180233590A1

公开(公告)日：2018-08-16

申请号：US15923787

申请日：2018-03-16

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≥5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

公开(公告)号：US09837519B2

公开(公告)日：2017-12-05

申请号：US15345880

申请日：2016-11-08

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/522 ,  H01L29/15 ,  H01L29/417 ,  H01L29/861 ,  H01L29/20 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

公开(公告)号：US09306051B2

公开(公告)日：2016-04-05

申请号：US14590433

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao Miura ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件在其衬底上具有第一缓冲层（GaN），第二缓冲层（AlGaN），沟道层和势垒层，穿过阻挡层并到达沟道层中间的沟槽 通过栅极绝缘膜放置在沟槽中的栅电极，以及分别形成在栅极两侧的源电极和漏电极。 通过到达第一缓冲层的通孔中的耦合部分，缓冲层和源电极彼此电耦合。 由于在这两个缓冲层之间的界面附近产生的二维电子气，所以半导体器件可以具有增加的阈值电压和改善的常关特性。

公开(公告)号：US20150221757A1

公开(公告)日：2015-08-06

申请号：US14604796

申请日：2015-01-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L23/522 ,  H01L29/15

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

Abstract translation: 提高了半导体器件的特性。 半导体器件被配置为提供穿透阻挡层的沟槽，并且到达n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分，其中 形成在基板上方，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分彼此电耦合。 p型层和源电极通过到达p型层的连接部分彼此电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

公开(公告)号：US20150115323A1

公开(公告)日：2015-04-30

申请号：US14582624

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device including a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap wider than that of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer to reach the middle of the first nitride semiconductor layer, a conductive film formed at a corner portion corresponding to an end portion of a bottom surface of the trench and a gate electrode disposed via a gate insulating film inside the trench including a region on the conductive film.

Abstract translation: 一种半导体器件，包括在衬底上形成的第一氮化物半导体层，形成在第一氮化物半导体层上并且具有比第一氮化物半导体层的带隙宽的带隙的第二氮化物半导体层，穿过第二氮化物半导体层的沟槽 为了到达第一氮化物半导体层的中间，形成在对应于沟槽的底面的端部的角部的导电膜和经沟槽内部的栅极绝缘膜设置的栅电极，包括导电 电影。

公开(公告)号：US20140239311A1

公开(公告)日：2014-08-28

申请号：US14188462

申请日：2014-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/20

CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

Abstract translation: 半导体器件包括缓冲层，沟道层和在衬底上形成的势垒层，穿过势垒层的沟槽到达沟道层的中间，以及通过栅极绝缘膜设置在沟槽内的栅电极。 沟道层含有n型杂质，位于缓冲层侧的沟道层的区域的n型杂质浓度大于位于势垒层侧的沟道层的区域，并且形成缓冲层 的氮化物半导体具有比沟道层宽的带隙。 沟道层由GaN制成，缓冲层由AlGaN制成。 沟道层具有含有中等浓度的n型杂质的沟道下层和形成在其上的主沟道层并且含有低浓度的n型杂质。

公开(公告)号：US10461159B2

公开(公告)日：2019-10-29

申请号：US15966773

申请日：2018-04-30

Applicant: Renesas Electronics Corporation

Inventor： Hironobu Miyamoto ,  Tatsuo Nakayawa ,  Yasuhiro Okamoto ,  Atsushi Tsuboi

IPC: H01L21/00 ,  H01L29/20 ,  H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/43 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40

Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

公开(公告)号：US10199476B2

公开(公告)日：2019-02-05

申请号：US15841676

申请日：2017-12-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/207

Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

公开(公告)号：US09984884B2

公开(公告)日：2018-05-29

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/04 ,  H01L29/778 ,  H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US09660045B2

公开(公告)日：2017-05-23

申请号：US15079879

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Toshiyuki Takewaki ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/51 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L23/29 ,  H01L23/31 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.