公开(公告)号：US11049786B2

公开(公告)日：2021-06-29

申请号：US16575045

申请日：2019-09-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita Tsuchiya ,  Shuuichi Kariyazaki ,  Takashi Kikuchi ,  Michiaki Sugiyama ,  Yusuke Tanuma

IPC: H01L23/36 ,  H01L23/40 ,  H01L23/538 ,  H01L25/18

Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.

公开(公告)号：US09129828B2

公开(公告)日：2015-09-08

申请号：US14027187

申请日：2013-09-14

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线布线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。

公开(公告)号：US20140077391A1

公开(公告)日：2014-03-20

申请号：US14027187

申请日：2013-09-14

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线布线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。

公开(公告)号：US08541261B2

公开(公告)日：2013-09-24

申请号：US13666125

申请日：2012-11-01

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Tomoaki Hashimoto ,  Tatsuya Hirai

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/565 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.

Abstract translation: 与微电脑芯片（半导体芯片）的焊盘（电极焊盘）电连接的端子（接合引线）配置在周边部分侧的焊盘上的凸起电极（导电部件）用密封树脂（密封体）密封。 此后，密封树脂被部分地研磨（去除），使得每个凸起电极的一部分露出。 在研磨步骤之后，执行从密封树脂的前表面突出每个凸起电极的一部分的步骤。

公开(公告)号：US20150340342A1

公开(公告)日：2015-11-26

申请号：US14818145

申请日：2015-08-04

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线配线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。