公开(公告)号：US09377825B2

公开(公告)日：2016-06-28

申请号：US14296552

申请日：2014-06-05

Applicant: Renesas Electronics Corporation

Inventor： Minoru Shinohara ,  Makoto Araki ,  Michiaki Sugiyama

IPC: H01L23/50 ,  G06F1/18 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G06F1/185 ,  G11C5/02 ,  G11C5/063 ,  H01L23/5388 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract translation: 存储卡具有布线板，堆叠在布线板的主表面上的四个存储芯片，以及安装在最上层的存储芯片的表面上的控制器芯片和插入器。 存储芯片堆叠在布线板的表面上，使得它们的长边沿着与布线板的长边方向相同的方向。 最下层的存储芯片以错位的方式在朝向存储卡前端的方向上以预定的距离安装在布线板上，以便不与布线板的焊盘重叠。 堆叠在最下层的存储芯片上的三个存储芯片被布置成使得它们在其上形成焊盘的短边位于存储卡的前端。

公开(公告)号：US11049786B2

公开(公告)日：2021-06-29

申请号：US16575045

申请日：2019-09-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita Tsuchiya ,  Shuuichi Kariyazaki ,  Takashi Kikuchi ,  Michiaki Sugiyama ,  Yusuke Tanuma

IPC: H01L23/36 ,  H01L23/40 ,  H01L23/538 ,  H01L25/18

Abstract: The semiconductor device includes a wiring substrate, a first and second semiconductor chips, and the heat sink. The wiring substrate has a first surface. The first and second semiconductor chips are disposed on the first surface. The heat sink is disposed on the first surface so as to cover the first semiconductor chip. The heat sink has a second surface and the third surface opposite the first surface. The second surface faces the first surface. The heat sink has a first cut-out portion. The first cut-out portion is formed at a position overlapping with the second semiconductor chip in plan view, and penetrates the heat sink in a direction from the third surface toward the second surface. The second surface is joined to at least four corners of the first surface.

公开(公告)号：US20160204082A1

公开(公告)日：2016-07-14

申请号：US15075128

申请日：2016-03-19

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L25/065

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract translation: 在通过将包括小直径的半导体芯片和具有大直径的半导体芯片的芯片层叠体安装在基板的顶表面上而形成的半导体器件中，防止了过度的应力被添加到两个半导体芯片的接头 。 通过在支撑基板上安装具有大直径的第一半导体芯片，然后在第一半导体芯片上安装具有小直径的第二半导体芯片，可以：抑制安装在第一半导体芯片上的第二半导体芯片的倾斜和不稳定性 半导体芯片; 并且因此抑制过多的应力被添加到第一半导体芯片和第二半导体芯片的接头。

公开(公告)号：US20140312498A1

公开(公告)日：2014-10-23

申请号：US14229981

申请日：2014-03-30

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Jumpei Konno

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/13014 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48111 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/0052 ,  H05K3/326 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0665

Abstract: To provide a semiconductor device having improved reliability.In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.

Abstract translation: 提供具有提高的可靠性的半导体器件。 在BGA的布线基板中，绝缘层上具有多个接合引线。 绝缘层由具有玻璃布的预浸料和不具有玻璃布的树脂层构成。 预浸料在其上具有树脂层。 接合引线直接配置在软树脂层上，由此软树脂层支撑。 当在倒装芯片接合期间对每个接合引线施加负载时，树脂层下沉，由此可以放松施加到半导体芯片的应力。

公开(公告)号：US09818678B2

公开(公告)日：2017-11-14

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

公开(公告)号：US20140183759A1

公开(公告)日：2014-07-03

申请号：US14138164

申请日：2013-12-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L23/00 ,  H01L23/49

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/743 ,  H01L24/97 ,  H01L2224/10175 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract translation: 提高了半导体器件的可靠性。 形成在布线基板中的芯片安装面上的多个端子中的每一个在平面图中具有窄宽度部分布置在相邻的宽幅部分之间的形状。 此外，形成在安装在布线基板上的半导体芯片上的多个突起电极中的每一个的前端面的中心布置在与平面图中的窄宽度部分重叠的位置，并且多个端子和 多个突出电极经由焊料构件彼此电连接。

公开(公告)号：US20140065767A1

公开(公告)日：2014-03-06

申请号：US13969542

申请日：2013-08-17

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract translation: 在通过将包括小直径的半导体芯片和具有大直径的半导体芯片的芯片层叠体安装在基板的顶表面上而形成的半导体器件中，防止了过度的应力被添加到两个半导体芯片的接头 。 通过在支撑基板上安装具有大直径的第一半导体芯片，然后在第一半导体芯片上安装具有小直径的第二半导体芯片，可以：抑制安装在第一半导体芯片上的第二半导体芯片的倾斜和不稳定性 半导体芯片; 并且因此抑制过多的应力被添加到第一半导体芯片和第二半导体芯片的接头。

公开(公告)号：US09640414B2

公开(公告)日：2017-05-02

申请号：US15075128

申请日：2016-03-19

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US09455240B2

公开(公告)日：2016-09-27

申请号：US14138164

申请日：2013-12-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/743 ,  H01L24/97 ,  H01L2224/10175 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.

Abstract translation: 提高了半导体器件的可靠性。 形成在布线基板中的芯片安装面上的多个端子中的每一个在平面图中具有窄宽度部分布置在相邻的宽幅部分之间的形状。 此外，形成在安装在布线基板上的半导体芯片上的多个突起电极中的每一个的前端面的中心布置在与平面图中的窄宽度部分重叠的位置，并且多个端子和 多个突出电极经由焊料构件彼此电连接。

公开(公告)号：US09355869B2

公开(公告)日：2016-05-31

申请号：US13969542

申请日：2013-08-17

Applicant: Renesas Electronics Corporation

Inventor： Michiaki Sugiyama ,  Nobuhiro Kinoshita

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83104 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2224/19 ,  H01L2224/05552

Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract translation: 在通过将包括小直径的半导体芯片和具有大直径的半导体芯片的芯片层叠体安装在基板的顶表面上而形成的半导体器件中，防止了过度的应力被添加到两个半导体芯片的接头 。 通过在支撑基板上安装具有大直径的第一半导体芯片，然后在第一半导体芯片上安装具有小直径的第二半导体芯片，可以：抑制安装在第一半导体芯片上的第二半导体芯片的倾斜和不稳定性 半导体芯片; 并且因此抑制过多的应力被添加到第一半导体芯片和第二半导体芯片的接头。