公开(公告)号：US09818815B2

公开(公告)日：2017-11-14

申请号：US14961622

申请日：2015-12-07

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Hiromi Shigihara ,  Hisao Shigihara

IPC: H01L49/02 ,  H01L23/495 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.

公开(公告)号：US09805950B2

公开(公告)日：2017-10-31

申请号：US15462583

申请日：2017-03-17

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Takayuki Igarashi

IPC: H01L29/76 ,  H01L21/3205 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/66 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

公开(公告)号：US20180069073A1

公开(公告)日：2018-03-08

申请号：US15799772

申请日：2017-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Hiromi Shigihara ,  Hisao SHIGIHARA

IPC: H01L49/02 ,  H01L27/12 ,  H01L27/06 ,  H01L23/00 ,  H01L23/522 ,  H01L23/495

CPC classification number: H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.

公开(公告)号：US09536828B2

公开(公告)日：2017-01-03

申请号：US14651643

申请日：2012-12-19

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Hirokazu Nagase ,  Takuo Funaya

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/065 ,  H01L27/06 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/645 ,  H01L23/66 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L27/0688 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6.

Abstract translation: 在半导体衬底上形成线圈CL5和CL6以及焊盘PD5，PD6和PD7。 线圈CL5和线圈CL6串联地电连接在焊盘PD5和焊盘PD6之间，并且焊盘PD7电连接在线圈CL5和线圈CL6之间。 磁耦合到线圈CL5的线圈形成在线圈CL5的正下方，与线圈CL6磁性耦合的线圈形成在线圈CL6的正下方，并且它们串联连接。 当线圈CL5和CL6正下方的串联连接的线圈中流过电流时，线圈CL5和CL6中流过的感应电流的方向在线圈CL5和CL6中彼此相对。

公开(公告)号：US20160087025A1

公开(公告)日：2016-03-24

申请号：US14961622

申请日：2015-12-07

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Hiromi Shigihara ,  Hisao SHIGIHARA

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.

Abstract translation: 半导体器件包括具有主表面的半导体衬底; 形成在主表面上的第一线圈; 形成在所述第一线圈上并具有第一主表面的第一绝缘膜; 形成在第一绝缘膜的第一主表面上并具有第二主表面的第二绝缘膜; 以及形成在所述第二绝缘膜的所述第二主表面上的第二线圈，其中所述第一绝缘膜的所述第一主表面具有形成有所述第二绝缘膜的第一区域，并且在第一区域中具有第一区域， 平面图，并且其中第二绝缘膜在平面图中被第二区域包围。

公开(公告)号：US11063009B2

公开(公告)日：2021-07-13

申请号：US15888846

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenji Sakata ,  Toshihiko Akiba ,  Takuo Funaya ,  Hideaki Tsuchiya ,  Yuichi Yoshida

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

Abstract: There is a need to improve reliability of the semiconductor device.
A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

公开(公告)号：US09653396B2

公开(公告)日：2017-05-16

申请号：US14777454

申请日：2013-03-25

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Takayuki Igarashi

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/00 ,  H01L27/06 ,  H01L21/66 ,  H01L21/3205 ,  H01L49/02 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

公开(公告)号：US20160027732A1

公开(公告)日：2016-01-28

申请号：US14418116

申请日：2014-01-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki Igarashi ,  Takuo Funaya

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/16

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

Abstract translation: 提高了半导体器件的特性。 半导体器件包括形成在层间绝缘体IL2上的线圈CL1和形成在层间绝缘体IL2上的布线M2，形成在层间绝缘体IL3上的布线M3，以及形成在层间绝缘体IL4上的线圈CL2和布线M4。 此外，线圈CL2和布线M4之间的距离DM4比线圈CL2和布线M3之间的距离DM3（DM4> DM3）长。 此外，线圈CL2和布线M3之间的距离DM3被设定为长于位于线圈CL1和线圈之间的层间绝缘体IL3的膜厚和层间绝缘体IL4的膜厚之和 CL2。 以这种方式，可以提高线圈CL2和布线M4之间的绝缘耐受电压，其中趋于发生高电压差。 此外，形成了包围周边电路形成区域1B的变压器形成区域1A和密封环形成区域1C，以提高耐湿性。

公开(公告)号：US09219108B2

公开(公告)日：2015-12-22

申请号：US14625390

申请日：2015-02-18

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Hiromi Shigihara ,  Hisao Shigihara

IPC: H01L49/02 ,  H01L23/495 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device including a semiconductor substrate having a main surface; a first insulating layer formed on the main surface and having a first main surface, the first main surface including a first region and a second region without the first area; a first coil formed on the first region of the first insulating layer; a plurality of first wirings formed on the second region of the first insulating layer; a second insulating layer formed on the first coil and on the first wirings, the second insulating layer having a second main surface; a third insulating layer formed on the second main surface above the first region of the first insulating layer and having a third main surface; and a second coil formed on the third main surface of the third insulating layer.

Abstract translation: 一种半导体器件，包括具有主表面的半导体衬底; 形成在所述主表面上并具有第一主表面的第一绝缘层，所述第一主表面包括第一区域和没有所述第一区域的第二区域; 形成在所述第一绝缘层的所述第一区域上的第一线圈; 形成在所述第一绝缘层的所述第二区域上的多个第一布线; 形成在所述第一线圈和所述第一布线上的第二绝缘层，所述第二绝缘层具有第二主表面; 第三绝缘层，形成在所述第一绝缘层的所述第一区域上方的所述第二主表面上，并具有第三主表面; 以及形成在第三绝缘层的第三主表面上的第二线圈。

公开(公告)号：US08987861B2

公开(公告)日：2015-03-24

申请号：US14106569

申请日：2013-12-13

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Hiromi Shigihara ,  Hisao Shigihara

IPC: H01L49/02 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0617 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06102 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced.

Abstract translation: 提高了半导体器件的特性。 半导体器件具有形成在下层电感器上方的层叠绝缘膜。 该层压绝缘膜包括第一聚酰亚胺膜和形成在第一聚酰亚胺膜上的第二聚酰亚胺膜，并且在第一聚酰亚胺膜和第二聚酰亚胺膜之间具有第二步骤。 在层叠绝缘膜上形成上层电感器。 由于采用第一和第二聚酰亚胺膜的这种叠层结构，所以可以增加下层和上层电感器之间的绝缘膜的膜厚度，从而可以提高耐受电压。 此外，可以减少由于曝光不良引起的凹陷或剥离的发生，并且还可以减少由于阶梯断开而导致的Cu（铜）种子层的步骤断开或电镀缺陷。