公开(公告)号：US20140353746A1

公开(公告)日：2014-12-04

申请号：US14291724

申请日：2014-05-30

Applicant: ROHM CO., LTD.

Inventor： Yasushi HAMAZAWA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/76232 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211

Abstract: A semiconductor device of the present invention includes a semiconductor layer, a source region and a drain region formed in a surface of the semiconductor layer, both having a first conductivity type, a plurality of gate trenches each formed so as to extend across the source region and the drain region, in a plan view observed in a direction of a normal to the surface of the semiconductor layer, a channel region of a first conductivity type made of the semiconductor layer sandwiched by the gate trenches adjacent to each other, having a channel length along a direction extending from the drain region to the source region, and a gate electrode buried in the gate trench via a gate insulating film, and the channel region has a thickness in the plan view not more than two times a width of a depletion layer to be generated due to a built-in potential between the channel region and the gate electrode.

Abstract translation: 本发明的半导体器件包括形成在半导体层的表面中的半导体层，源极区和漏极区，它们都具有第一导电型，多个栅极沟槽形成为跨越源区 以及漏极区域，在与半导体层的表面的法线方向观察的平面图中，形成有由彼此相邻的栅极沟槽夹在中间的半导体层构成的第一导电类型的沟道区域，具有沟道 沿着从漏极区域延伸到源极区域的方向的长度;以及通过栅极绝缘膜掩埋在栅极沟槽中的栅电极，并且沟道区域在平面图中具有不大于耗尽宽度的两倍的厚度 由于沟道区域和栅电极之间的内置电位而产生的层。

公开(公告)号：US20160133742A1

公开(公告)日：2016-05-12

申请号：US14936666

申请日：2015-11-09

Applicant: ROHM CO., LTD.

Inventor： Hajime OKUDA ,  Yasushi HAMAZAWA

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/76895 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/535 ,  H01L23/544 ,  H01L24/06 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66734 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.

Abstract translation: 本发明的半导体器件包括其中形成栅极沟槽的半导体层，沿着栅极沟槽的内表面形成的栅极绝缘膜，通过栅极绝缘膜掩埋在栅极沟槽中的栅电极，并且 具有在下电极和上电极之间的中间绝缘膜彼此上下分离的下电极和上电极，以及形成在栅极沟槽中以穿过上电极的栅极接触 并且通过中间绝缘膜并且到达下电极并且将下电极和上电极电连接在一起。

公开(公告)号：US20230378345A1

公开(公告)日：2023-11-23

申请号：US18031015

申请日：2021-10-25

Applicant: ROHM CO., LTD.

Inventor： Yasushi HAMAZAWA

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/107 ,  H01L29/1033

Abstract: A semiconductor device includes a chip, a drain region, a source region formed at the surface layer portion of the main surface at a distance from the drain region, a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface, a drift region formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface, a gate insulating film having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface, and a gate electrode having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto second portion so as to partially expose second portion.

公开(公告)号：US20240204099A1

公开(公告)日：2024-06-20

申请号：US17909813

申请日：2021-03-03

Applicant: ROHM CO., LTD.

Inventor： Takeshi ISHIDA ,  Yasushi HAMAZAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0607 ,  H01L29/66681

Abstract: A semiconductor device 1 includes a p type substrate 4, an n type semiconductor layer 5 that is formed on the p type substrate, and a transistor 40 with the n type semiconductor layer as a drain, the transistor includes a p type well region 15 that is formed in a surface layer portion of the n type semiconductor layer and has an n type source contact region in a surface layer portion thereof and an n type drain contact region 14 that is formed in the surface layer portion of the n type semiconductor layer and is disposed at an interval from the p type well region 15, and, inside the n type semiconductor layer, a p type embedded layer 10 is formed below the p type well region.

公开(公告)号：US20180130587A1

公开(公告)日：2018-05-10

申请号：US15806282

申请日：2017-11-07

Applicant: ROHM CO., LTD.

Inventor： Bungo TANAKA ,  Yasushi HAMAZAWA

IPC: H01F17/00 ,  H01F5/00 ,  H01L49/02

CPC classification number: H01F17/0013 ,  H01F5/003 ,  H01F27/2804 ,  H01F27/2885 ,  H01F27/324 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L28/10

Abstract: An electronic component includes a first insulating layer, a high-voltage electrode formed on the first insulating layer, a low-voltage electrode formed on the first insulating layer so as to be spaced from the high-voltage electrode, and an uneven structure formed in a region between the high-voltage electrode and the low-voltage electrode along a surface of the first insulating layer.

公开(公告)号：US20240030276A1

公开(公告)日：2024-01-25

申请号：US18476339

申请日：2023-09-28

Applicant: ROHM CO., LTD.

Inventor： Keiji WADA ,  Yasushi HAMAZAWA

IPC: H03K17/687 ,  H01L25/16

CPC classification number: H01L28/60 ,  H03K17/687 ,  H01L25/16 ,  H01L2224/48195 ,  H01L2224/48175 ,  H01L24/48

Abstract: An isolator includes an insulation layer and a capacitor embedded in the insulation layer. The capacitor includes: a first electrode portion arranged in the insulation layer and connected to a first pad; a second electrode portion arranged in the insulation layer and connected to a second pad; and an intermediate electrode portion arranged in the insulation layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer, a second intermediate layer, and a connector connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by coupling the first electrode portion and the second electrode portion through the intermediate electrode portion.

公开(公告)号：US20240030105A1

公开(公告)日：2024-01-25

申请号：US18480233

申请日：2023-10-03

Applicant: ROHM CO., LTD.

Inventor： Yoshizo OSUMI ,  Yasushi HAMAZAWA ,  Tomohira KIKUCHI

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/49575 ,  H01L23/3135 ,  H01L24/48 ,  H01L23/49541 ,  H01L2224/48175

Abstract: A semiconductor device includes: a first die pad; a second die pad; a first semiconductor element on the first die pad; a second semiconductor element on the second die pad; an insulating element electrically connected to the first semiconductor element and the second semiconductor element and electrically insulating the first and second semiconductor elements from each other; a sealing resin covering the first semiconductor element, the second semiconductor element and the insulating element; and a support member on which the insulating element is mounted, where the support member includes an insulating portion containing a resin. The first die pad and the second die pad are spaced apart from each other in a first direction orthogonal to a thickness direction of the first semiconductor element. The support member is supported by at least one of the first die pad, the second die pad and the sealing resin.

公开(公告)号：US20240022246A1

公开(公告)日：2024-01-18

申请号：US18475216

申请日：2023-09-27

Applicant: ROHM CO., LTD.

Inventor： Keiji WADA ,  Yasushi HAMAZAWA

IPC: H03K17/691 ,  H03K17/06

CPC classification number: H03K17/691 ,  H03K17/063 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: An isolation transformer includes an insulation layer and a transformer. The transformer includes a first coil and a second coil embedded in the insulation layer. The first coil and the second coil are opposed to each other in a thickness-wise direction of the insulation layer. The first coil and the second coil include non-overlapping portions that do not overlap each other in the thickness-wise direction of the insulation layer.

公开(公告)号：US20220208674A1

公开(公告)日：2022-06-30

申请号：US17645357

申请日：2021-12-21

Applicant: ROHM Co., LTD.

Inventor： Keiji WADA ,  Yasushi HAMAZAWA

IPC: H01L23/522

Abstract: Provided is a gate driver that applies a gate voltage to a gate of a switching element, the gate driver including a low voltage circuit that operates when a first voltage is applied, a high voltage circuit that operates when a second voltage is applied, and an insulating chip, in which the insulating chip includes a substrate, an insulating layer, a first insulating element including a first conductor and a second conductor embedded into the insulating layer and arranged to face each other, and a second insulating element including a third conductor and a fourth conductor embedded into the insulating layer and arranged to face each other, and the low voltage circuit and the high voltage circuit are connected through the first insulating element and the second insulating element connected to each other in series and are configured to transmit signals through the first and second insulating elements.

公开(公告)号：US20170092759A1

公开(公告)日：2017-03-30

申请号：US15378224

申请日：2016-12-14

Applicant: ROHM CO., LTD.

Inventor： Hajime OKUDA ,  Yasushi HAMAZAWA

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/10 ,  H01L29/423 ,  H01L21/768 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/76895 ,  H01L21/823878 ,  H01L23/485 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/535 ,  H01L23/544 ,  H01L24/06 ,  H01L24/45 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66734 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.