公开(公告)号：US20070212820A1

公开(公告)日：2007-09-13

申请号：US11308167

申请日：2006-03-09

申请人： Rehan Choudhary ,  Benjamin Fasano ,  Sushumna Iruvanti ,  Daniel Reinhardt ,  Deborah Sylvester

发明人： Rehan Choudhary ,  Benjamin Fasano ,  Sushumna Iruvanti ,  Daniel Reinhardt ,  Deborah Sylvester

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  C08G2650/40 ,  C08L71/00 ,  H01L23/556 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2924/00014 ,  H01L2924/01084 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method and device comprising an easily reworkable alpha particle barrier is provided. The easily reworkable alpha particle barrier is applied in the space between the surface of the chip and the surface of the substrate, and reduces soft error rate (SER). Further, the easily reworkable alpha particle barrier material is chosen from the group of an organic material, a hydrocarbon, more specifically a polyalphaolefin (PAO) oil, and a polymer or filled polymer; wherein the polyalphaolefin oil has a viscosity below 1000 cSt (at 100° C.). The easily reworkable alpha particle barrier material can be used with multichip modules (MCM's) allowing easy device rework of one or more dies without affecting other dies on the same substrate.

摘要翻译： 提供了一种包括易于再加工的α粒子屏障的方法和装置。 在芯片的表面和基板的表面之间的空间中施加易于再加工的α粒子屏障，并且降低软错误率（SER）。 此外，易于再加工的α粒子阻挡材料选自有机材料，烃，更具体地是聚α-烯烃（PAO）油和聚合物或填充聚合物的组; 其中所述聚α-烯烃油的粘度低于1000cSt（在100℃）。 易于再加工的α粒子阻挡材料可以与多芯片模块（MCM）一起使用，允许一个或多个模具的简单的器件返工，而不会影响同一基板上的其他裸片。

公开(公告)号：US20080000988A1

公开(公告)日：2008-01-03

申请号：US11768312

申请日：2007-06-26

申请人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

发明人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US20060231633A1

公开(公告)日：2006-10-19

申请号：US10907761

申请日：2005-04-14

申请人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

发明人： Mukta Farooq ,  Benjamin Fasano ,  Jason Frankel ,  Harvey Hamel ,  Suresh Kadakia ,  David Long ,  Frank Pompeo ,  Sudipta Ray

IPC分类号： G06K19/06

CPC分类号： G06K19/07381 ,  H01L23/04 ,  H01L23/055 ,  H01L23/10 ,  H01L23/576 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/3011 ,  H05K1/0275 ,  H05K1/0306 ,  H05K1/144 ,  H05K2201/09263 ,  H05K2201/10151

摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

摘要翻译： 防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。 在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。 导电栅格结构被配置为检测穿透IC模块的尝试。

公开(公告)号：US20060099801A1

公开(公告)日：2006-05-11

申请号：US10904439

申请日：2004-11-10

申请人： Michael Cranmer ,  Michael Domitrovits ,  Benjamin Fasano ,  Harvey Hamel ,  Charles Ryan

发明人： Michael Cranmer ,  Michael Domitrovits ,  Benjamin Fasano ,  Harvey Hamel ,  Charles Ryan

IPC分类号： H01L21/4763

CPC分类号： H05K1/115 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K3/005 ,  H05K2201/09609 ,  H05K2201/09854 ,  H05K2203/1476 ,  H01L2924/00

摘要： An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.

摘要翻译： 一种集成电路结构和制造方法，其中所述方法包括在所述衬底的互连层中形成第一通孔，其中所述第一通孔包括第一尺寸直径; 以及在所述互连层中形成第二通孔，其中所述第二通孔包括第二尺寸直径，所述第二尺寸直径的尺寸大于所述第一尺寸直径，其中所述第二通孔包括不均匀的周长，并且其中所述基板被配置 以大约1:1的比例（即，大致相等的数量）第一和第二通孔。 第一和第二通孔是激光成形的或通过机械冲压和光刻中的任何一种形成。 第二通孔是通过顺序地形成多个部分重叠的通孔形成的，其尺寸和构造为具有第一尺寸直径。 第一和第二通孔布置成格栅以允许电子设备的布线。

公开(公告)号：US20060249827A1

公开(公告)日：2006-11-09

申请号：US10908277

申请日：2005-05-05

申请人： Benjamin Fasano ,  Brian Sundlof

发明人： Benjamin Fasano ,  Brian Sundlof

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/1627 ,  H01L2924/3025 ,  H01L2224/0401

摘要： A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.

摘要翻译： 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。

公开(公告)号：US20060202325A1

公开(公告)日：2006-09-14

申请号：US10906809

申请日：2005-03-08

申请人： Patrick Coico ,  David Edwards ,  Benjamin Fasano ,  Lewis Goldmann ,  Ellyn Ingalls ,  Michael June ,  Hilton Toy ,  Paul Zucco

发明人： Patrick Coico ,  David Edwards ,  Benjamin Fasano ,  Lewis Goldmann ,  Ellyn Ingalls ,  Michael June ,  Hilton Toy ,  Paul Zucco

IPC分类号： H01L23/34

CPC分类号： H01L23/4006 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4081 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

摘要： An integrated circuit chip mounting structure includes a chip carrier electrically connected to a circuit board with an integrated circuit chip mounted on the chip carrier. In addition, a thermally conductive device is thermally connected to the chip and a set of compressible support members are provided to transmit a portion of an applied compressive load from the thermally conductive device to the chip and chip carrier.

摘要翻译： 集成电路芯片安装结构包括芯片载体，其电连接到具有安装在芯片载体上的集成电路芯片的电路板。 此外，导热装置热连接到芯片，并且提供一组可压缩支撑构件以将施加的压缩载荷的一部分从导热装置传递到芯片和芯片载体。

公开(公告)号：US20060088997A1

公开(公告)日：2006-04-27

申请号：US10904138

申请日：2004-10-26

申请人： Benjamin Fasano ,  Richard Indyk ,  Kevin Prettyman

发明人： Benjamin Fasano ,  Richard Indyk ,  Kevin Prettyman

IPC分类号： H01L21/4763

CPC分类号： G01R31/2886 ,  G01R1/0466 ,  H01L21/486 ,  H01L21/6835

摘要： The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or holes in the outer few layers with the outer most layer not being filled with a conductor, such that a partially filled via or hole is produced. This effectively produces a smaller surface conductor feature, on which the semiconductor chip is temporarily attached, electrically tested, and subsequently removed using various methods, at forces much lower than normal chip removal processes require.

摘要翻译： 本发明提供一种用于制造用于半导体芯片老化测试和速度分选的临时芯片载体的方法。 通常由各种材料中的一种构成的多层基板或卡通过抵消外部几层中的导体填充的通孔或孔，其中最外层未填充有导体，从而使部分填充的通孔或 产生孔。 这有效地产生较小的表面导体特征，半导体芯片暂时附着，电学测试，并随后使用各种方法，以比正常的芯片去除工艺要求低得多的力除去。

公开(公告)号：US20070196953A1

公开(公告)日：2007-08-23

申请号：US11740962

申请日：2007-04-27

申请人： Benjamin Fasano ,  Brian Sundlof

发明人： Benjamin Fasano ,  Brian Sundlof

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/1627 ,  H01L2924/3025 ,  H01L2224/0401

摘要： A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.

摘要翻译： 叠层半导体装置具有至少一个附着在载体基板的第一侧的管芯。 第一电路化基板被附接到载体基板的第一侧并且以使得第一电路化基板用作电互连装置和散热盖的方式覆盖至少一个管芯。 第一电路化基板被进一步构造成便于通过至少一个冷却介质的横流而使至少一个管芯冷却。

公开(公告)号：US20060261467A1

公开(公告)日：2006-11-23

申请号：US10908615

申请日：2005-05-19

申请人： Evan Colgan ,  David Edwards ,  Benjamin Fasano ,  Kamal Sikka ,  Jeffrey Zitz ,  Wei Zou

发明人： Evan Colgan ,  David Edwards ,  Benjamin Fasano ,  Kamal Sikka ,  Jeffrey Zitz ,  Wei Zou

IPC分类号： H01L23/34

CPC分类号： H01L23/04 ,  H01L23/3675 ,  H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.

摘要翻译： 公开了一种包括用于包含热界面材料（TIM）并提高芯片冷却的芯片延伸的芯片封装以及相关方法。 特别地，芯片封装包括芯片，经由TIM耦合到芯片的冷却结构，并且芯片延伸部可热耦合到芯片的外边缘。 放置在芯片和冷却结构之间的TIM被芯片延伸部的热循环期间包含，从而可以抑制可在芯片和冷却结构之间移动的芯片边缘处的空隙形成。 芯片延伸还通过在冷却结构和芯片之间提供更大的热接触面积，并且如果需要，以比使用具有较低的晶片生产单位输出的较大模具的成本低得多的成本来改善侧向散热。