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32 条记录 (耗时 0.029 秒)

    Method of inducing stresses in the channel region of a transistor
    1.
    发明授权
    Method of inducing stresses in the channel region of a transistor 失效
    在晶体管的沟道区域中产生应力的方法

    公开(公告)号：US07528051B2

    公开(公告)日：2009-05-05

    申请号：US10846734

    申请日：2004-05-14

    申请人： Reza Arghavani ,  Zheng Yuan ,  Ellie Y. Yieh ,  Shankar Venkataraman ,  Nitin K. Ingle

    发明人： Reza Arghavani ,  Zheng Yuan ,  Ellie Y. Yieh ,  Shankar Venkataraman ,  Nitin K. Ingle

    IPC分类号： H01L21/76

    CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

    摘要： A method of fabricating a semiconductor device, where the method includes forming a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.

    摘要翻译： 一种制造半导体器件的方法，其中所述方法包括在衬底上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间传导电荷的沟道区域，形成与所述晶体管相邻的沟槽， 在衬底上和沟槽内，并对材料进行退火，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。 另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料 在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

    Gap filling with a composite layer
    3.
    发明授权
    Gap filling with a composite layer 失效
    间隙填充复合层

    公开(公告)号：US07033945B2

    公开(公告)日：2006-04-25

    申请号：US10857829

    申请日：2004-06-01

    申请人： Jeong Soo Byun ,  Zheng Yuan ,  Shankar Venkataraman ,  M. Ziaul Karim ,  Thanh N. Pham ,  Ellie Y. Yieh

    发明人： Jeong Soo Byun ,  Zheng Yuan ,  Shankar Venkataraman ,  M. Ziaul Karim ,  Thanh N. Pham ,  Ellie Y. Yieh

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76224

    摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.

    摘要翻译： 填充在基板上相邻的凸起表面之间形成的间隙的方法。 在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch
    4.
    发明授权
    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch 有权
    用于形成图案化硬掩模膜（RFP）的工艺顺序，无需光致抗蚀剂或干蚀刻

    公开(公告)号：US08153348B2

    公开(公告)日：2012-04-10

    申请号：US12034000

    申请日：2008-02-20

    申请人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    发明人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    IPC分类号： G03F7/26

    CPC分类号： G03F7/0757 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/6719 ,  H01L21/67207

    摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译： 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下，硬掩模层在沉积之后被烘烤或退火。 之后，硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。 在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

    PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH
    5.
    发明申请
    PROCESS SEQUENCE FOR FORMATION OF PATTERNED HARD MASK FILM (RFP) WITHOUT NEED FOR PHOTORESIST OR DRY ETCH 有权
    用于形成图形硬片（RFP）的过程序列，不需要用于光刻胶或干蚀刻

    公开(公告)号：US20090208880A1

    公开(公告)日：2009-08-20

    申请号：US12034000

    申请日：2008-02-20

    申请人： SRINIVAS D. NEMANI ,  Shankar Venkataraman ,  Ellie Y. Yieh

    发明人： SRINIVAS D. NEMANI ,  Shankar Venkataraman ,  Ellie Y. Yieh

    IPC分类号： G03F7/00 ,  C23F1/00

    CPC分类号： G03F7/0757 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/6719 ,  H01L21/67207

    摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译： 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下，硬掩模层在沉积之后被烘烤或退火。 之后，硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。 在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

    Internal balanced coil for inductively coupled high density plasma processing chamber
    9.
    发明授权
    Internal balanced coil for inductively coupled high density plasma processing chamber 有权
    用于电感耦合高密度等离子体处理室的内部平衡线圈

    公开(公告)号：US07789993B2

    公开(公告)日：2010-09-07

    申请号：US11670662

    申请日：2007-02-02

    申请人： Robert Chen ,  Canfeng Lai ,  Xinglong Chen ,  Weiyi Luo ,  Zhong Qiang Hua ,  Siqing Lu ,  Muhammad Rasheed ,  Qiwei Liang ,  Dmitry Lubomirsky ,  Ellie Y. Yieh

    发明人： Robert Chen ,  Canfeng Lai ,  Xinglong Chen ,  Weiyi Luo ,  Zhong Qiang Hua ,  Siqing Lu ,  Muhammad Rasheed ,  Qiwei Liang ,  Dmitry Lubomirsky ,  Ellie Y. Yieh

    IPC分类号： C23C16/00 ,  H01L21/306

    CPC分类号： H01J37/321

    摘要： A coil is provided for use in a semiconductor processing system to generate a plasma with a magnetic field in a chamber. The coil comprises a first coil segment, a second coil segment and an internal balance capacitor. The first coils segment has a first end and a second end. The first end of the coil segment is adapted to connect to a power source. The second coil segment has a first and second end. The second end of the first coil segment is adapted to connect to an external balance capacitor. The internal balance capacitor is connected in series between the second end of the first coil segment and the first end of the second coil segment. The internal balance capacitor and the coil segments are adapted to provide a voltage peak along the first coil segment substantially aligned with a virtual ground along the second coil segment.

    摘要翻译： 提供一种用于半导体处理系统中的线圈以在腔室中产生具有磁场的等离子体。 线圈包括第一线圈段，第二线圈段和内部平衡电容器。 第一线圈段具有第一端和第二端。 线圈段的第一端适于连接到电源。 第二线圈段具有第一和第二端。 第一线圈段的第二端适于连接到外部平衡电容器。 内部平衡电容器串联连接在第一线圈段的第二端和第二线圈段的第一端之间。 内部平衡电容器和线圈段适于沿着第一线圈段提供基本上与第二线圈段的虚拟接地对准的电压峰值。