-
公开(公告)号：US06222145B1
公开(公告)日：2001-04-24
申请号：US09182333
申请日：1998-10-29
IPC分类号： B07C5344
CPC分类号： B07C5/34 , Y10S209/938
摘要： A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.
摘要翻译： 集成电路芯片分类方法。 在半导体芯片中检测到至少一个物理缺陷。 基于物理缺陷对半导体芯片进行分类。
-
2.发明授权Method and system for dicing wafers, and semiconductor structures incorporating the products thereof 失效用于切割晶片的方法和系统，以及结合其产品的半导体结构公开(公告)号：US06915795B2
公开(公告)日：2005-07-12
申请号：US10448305
申请日：2003-05-30
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： B23D59/00 , B28D5/02 , H01L21/301 , H01L21/607 , H01L21/78 , H01L29/06 , B28D1/04
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
摘要翻译： 一种用于切割半导体晶片的方法和系统，其提供具有大大减小的背面切屑和开裂的结构，以及增加的模具强度。 还包括从根据本发明切割的晶片获得的半导体芯片结构。
-
3.发明授权公开(公告)号：US06600213B2
公开(公告)日：2003-07-29
申请号：US09855617
申请日：2001-05-15
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： H01L2906
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.
摘要翻译： 通过以下方式提供具有大大降低的背面切屑和开裂的半导体结构以及增加的模具强度，具有诸如另一半导体芯片的载体的紧凑组件和对封装损坏的抵抗性的切割芯片， 的芯片。 在多芯片结构中也有类似的优点。
-
4.发明授权公开(公告)号：US06271102B1
公开(公告)日：2001-08-07
申请号：US09032151
申请日：1998-02-27
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： H01L21301
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
-
5.发明授权公开(公告)号：US07915732B2
公开(公告)日：2011-03-29
申请号：US12164447
申请日：2008-06-30
申请人： Stephen P. Ayotte , Jeffrey D. Gilbert , David J. Hill , Ronald L. Mendelson , Timothy M. Sullivan
发明人： Stephen P. Ayotte , Jeffrey D. Gilbert , David J. Hill , Ronald L. Mendelson , Timothy M. Sullivan
CPC分类号： H05K3/303 , H01L24/13 , H01L24/16 , H01L2224/10175 , H01L2224/16 , H01L2224/81801 , H01L2924/01322 , H01L2924/14 , H05K3/3436 , H05K3/3452 , H05K2201/2018 , H05K2201/2036 , Y02P70/613
摘要： Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.
摘要翻译： 制造方法和如此制造的结构，用于制造集成电路（IC）芯片封装而不形成微焊球。 在一个实施例中，一种方法可以包括将由有机材料制成的固体栅格放置在IC芯片和衬底之间。 栅格在多个受控崩溃芯片连接中的每一个之间提供物理屏障，从而防止在它们之间形成微焊球，从而提高芯片性能和可靠性。
-
6.发明申请PRODUCTION OF INTEGRATED CIRCUIT CHIP PACKAGES PROHIBITING FORMATION OF MICRO SOLDER BALLS 有权集成电路芯片封装的生产禁止形成微型焊枪公开(公告)号：US20090321914A1
公开(公告)日：2009-12-31
申请号：US12164447
申请日：2008-06-30
申请人： Stephen P. Ayotte , Jeffrey D. Gilbert , David J. Hill , Ronald L. Mendelson , Timothy M. Sullivan
发明人： Stephen P. Ayotte , Jeffrey D. Gilbert , David J. Hill , Ronald L. Mendelson , Timothy M. Sullivan
CPC分类号： H05K3/303 , H01L24/13 , H01L24/16 , H01L2224/10175 , H01L2224/16 , H01L2224/81801 , H01L2924/01322 , H01L2924/14 , H05K3/3436 , H05K3/3452 , H05K2201/2018 , H05K2201/2036 , Y02P70/613
摘要： Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.
摘要翻译： 制造方法和如此制造的结构，用于制造集成电路（IC）芯片封装而不形成微焊球。 在一个实施例中，一种方法可以包括将由有机材料制成的固体栅格放置在IC芯片和衬底之间。 栅格在多个受控崩溃芯片连接中的每一个之间提供物理屏障，从而防止在它们之间形成微焊球，从而提高芯片性能和可靠性。
-
公开(公告)号：US06368881B1
公开(公告)日：2002-04-09
申请号：US09516445
申请日：2000-02-29
申请人： Donald W. Brouillette , Thomas G. Ference , Harold G. Linde , Michael S. Hibbs , Ronald L. Mendelson
发明人： Donald W. Brouillette , Thomas G. Ference , Harold G. Linde , Michael S. Hibbs , Ronald L. Mendelson
IPC分类号： H01L2100
CPC分类号： H01L22/26
摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.
-
公开(公告)号：US6153536A
公开(公告)日：2000-11-28
申请号：US262601
申请日：1999-03-04
CPC分类号： H01L21/6836 , B24B1/00 , B24B41/06 , B24B7/228 , H01L2221/68327
摘要： A method for manufacturing a low profile semiconductor chip, includes fabricating a semiconductor device on a semiconductor wafer, grinding, with a grinding tool, a backside of the semiconductor wafer to reduce a thickness thereof, and with the wafer in the grinding tool, providing a support structure on the ground backside of the wafer.
摘要翻译： 一种用于制造低剖面半导体芯片的方法，包括在半导体晶片上制造半导体器件，用研磨工具，半导体晶片的背面研磨以减小其厚度，并且与研磨工具中的晶片一起提供 支撑结构在晶片的背面。
-
公开(公告)号：US07134933B2
公开(公告)日：2006-11-14
申请号：US11058537
申请日：2005-02-15
申请人： Donald W. Brouillette , Thomas G. Ference , Harold G Linde , Michael S. Hibbs , Ronald L. Mendelson
发明人： Donald W. Brouillette , Thomas G. Ference , Harold G Linde , Michael S. Hibbs , Ronald L. Mendelson
CPC分类号： H01L22/26
摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.
-
公开(公告)号：US06887126B2
公开(公告)日：2005-05-03
申请号：US10012707
申请日：2001-12-07
申请人： Donald W. Brouillette , Thomas G. Ference , Harold G. Linde , Michael S. Hibbs , Ronald L. Mendelson
发明人： Donald W. Brouillette , Thomas G. Ference , Harold G. Linde , Michael S. Hibbs , Ronald L. Mendelson
CPC分类号： H01L22/26
摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.021 秒)
