公开(公告)号：US06915795B2

公开(公告)日：2005-07-12

申请号：US10448305

申请日：2003-05-30

申请人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

IPC分类号： B23D59/00 ,  B28D5/02 ,  H01L21/301 ,  H01L21/607 ,  H01L21/78 ,  H01L29/06 ,  B28D1/04

CPC分类号： H01L24/85 ,  B23D59/002 ,  B28D5/022 ,  H01L21/78 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/78302 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T83/0259 ,  Y10T83/0378 ,  Y10T83/0581 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

摘要翻译： 一种用于切割半导体晶片的方法和系统，其提供具有大大减小的背面切屑和开裂的结构，以及增加的模具强度。 还包括从根据本发明切割的晶片获得的半导体芯片结构。

公开(公告)号：US06600213B2

公开(公告)日：2003-07-29

申请号：US09855617

申请日：2001-05-15

申请人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

IPC分类号： H01L2906

CPC分类号： H01L24/85 ,  B23D59/002 ,  B28D5/022 ,  H01L21/78 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/78302 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T83/0259 ,  Y10T83/0378 ,  Y10T83/0581 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.

摘要翻译： 通过以下方式提供具有大大降低的背面切屑和开裂的半导体结构以及增加的模具强度，具有诸如另一半导体芯片的载体的紧凑组件和对封装损坏的抵抗性的切割芯片， 的芯片。 在多芯片结构中也有类似的优点。

公开(公告)号：US06271102B1

公开(公告)日：2001-08-07

申请号：US09032151

申请日：1998-02-27

申请人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Robert F. Cook ,  Thomas G. Ference ,  Wayne J. Howell ,  Eric G. Liniger ,  Ronald L. Mendelson

IPC分类号： H01L21301

CPC分类号： H01L24/85 ,  B23D59/002 ,  B28D5/022 ,  H01L21/78 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/78302 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T83/0259 ,  Y10T83/0378 ,  Y10T83/0581 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

公开(公告)号：US07134933B2

公开(公告)日：2006-11-14

申请号：US11058537

申请日：2005-02-15

申请人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

IPC分类号： B24B49/00 ,  B24B51/00

CPC分类号： H01L22/26

摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

公开(公告)号：US06887126B2

公开(公告)日：2005-05-03

申请号：US10012707

申请日：2001-12-07

申请人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G. Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G. Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

IPC分类号： H01L21/66 ,  B24B49/00 ,  B24B51/00

CPC分类号： H01L22/26

摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

公开(公告)号：US06368881B1

公开(公告)日：2002-04-09

申请号：US09516445

申请日：2000-02-29

申请人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G. Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

发明人： Donald W. Brouillette ,  Thomas G. Ference ,  Harold G. Linde ,  Michael S. Hibbs ,  Ronald L. Mendelson

IPC分类号： H01L2100

CPC分类号： H01L22/26

摘要： A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

公开(公告)号：US06265771B1

公开(公告)日：2001-07-24

申请号：US09238492

申请日：1999-01-27

申请人： Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

发明人： Thomas G. Ference ,  Wayne J. Howell ,  Edmund J. Sprogis

IPC分类号： H01L2310

CPC分类号： H01L23/4334 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An apparatus for simultaneously removing heat from two surfaces of a semiconductor structure includes a heat sink mounted to a front surface and a heat sink mounted to a back surface of the semiconductor structure. The structure can be two chips mounted in face-to-face arrangement, and the heat sinks remove heat from back surfaces of both chips.

摘要翻译： 同时从半导体结构的两个表面去除热量的装置包括安装到前表面的散热器和安装到半导体结构的后表面的散热片。 该结构可以是以面对面布置安装的两个芯片，并且散热器从两个芯片的背面去除热量。

公开(公告)号：US06611050B1

公开(公告)日：2003-08-26

申请号：US09538636

申请日：2000-03-30

申请人： Thomas G. Ference ,  Wayne J. Howell ,  William R. Tonti ,  Richard Q. Williams

发明人： Thomas G. Ference ,  Wayne J. Howell ,  William R. Tonti ,  Richard Q. Williams

IPC分类号： H01L2302

CPC分类号： H01L23/5388 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/3185 ,  H01L24/03 ,  H01L24/11 ,  H01L25/0655 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/11312 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/16054 ,  H01L2224/16105 ,  H01L2224/16137 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention provides a method of forming a low profile chip interconnection, and the interconnection so formed. A recessed contact area is formed at an edge of the wafer. A conductive material is deposited within the adjacent contact areas of each recess, thereby electrically connecting the two chips. The recess may have substantially perpendicular sides, or sloped sides.

摘要翻译： 本发明提供一种形成低轮廓芯片互连的方法，以及形成的互连。 在晶片的边缘处形成凹陷接触区域。 导电材料沉积在每个凹槽的相邻接触区域内，从而电连接两个芯片。 凹部可以具有大致垂直的侧面或倾斜的侧面。

公开(公告)号：US06426241B1

公开(公告)日：2002-07-30

申请号：US09439112

申请日：1999-11-12

申请人： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

发明人： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

IPC分类号： H01L2144

CPC分类号： H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H05K3/101 ,  H05K3/107 ,  H05K3/3421 ,  H05K2201/0305 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2203/128 ,  H01L2924/00

摘要： A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

摘要翻译： 提供了一种用于在基板中形成三维电路的方法，用于形成导电迹线和通孔触点。 在该方法中，首先提供由基本绝缘材料形成的基板，然后形成在基板的顶表面中的沟槽和孔，然后用导电材料（例如焊料）填充凹槽和孔。 该方法可以以低成本进行，以通过使用注射成型焊接技术或熔融焊料筛选技术来填充槽和孔来产生高质量的电路基板。 衬底中的凹槽和孔可以通过各种技术形成，例如化学蚀刻，物理加工和热冲压。

公开(公告)号：US6030855A

公开(公告)日：2000-02-29

申请号：US246435

申请日：1999-02-08

申请人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

发明人： Claude L. Bertin ,  Thomas G. Ference ,  Wayne J. Howell

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/485 ,  H01L23/50 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14

摘要： A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.

摘要翻译： 半导体结构包括两个半导体芯片的堆叠。 芯片的边缘形成堆叠的侧表面。 绝缘和粘合剂位于芯片之间，并且其中一个芯片上的导线接触电路通过绝缘体延伸到侧表面。 第一导体接触侧面上的导线。 第一导线与导线自对准并在侧面上方延伸。 第一导体便于侧表面上与半导体芯片绝缘的垫或连接器。 自对准的第一导体是电镀或无电镀金属。