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公开(公告)号：US6043724A
公开(公告)日：2000-03-28
申请号：US15231
申请日：1998-01-29
CPC分类号： H04B15/00 , H03L7/099 , H01L2224/16225 , H01L2924/15312
摘要： Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.
摘要翻译： 描述了用于电力噪声敏感电路的中高频模块（片外）/片上功率噪声滤波器的新颖实现。 为了实现这一点，使用二阶低通方法。 第一级电容器位于模块（片外）上，第二级电容器在片上实现。
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公开(公告)号：US07742315B2
公开(公告)日：2010-06-22
申请号：US11282041
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Gerald J. Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring.In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译： 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。
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公开(公告)号：US20070111576A1
公开(公告)日：2007-05-17
申请号：US11282041
申请日：2005-11-17
申请人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
发明人： Wiren Becker , Bruce Chamberlin , Gerald Fahr , Roland Frech , Dierk Kaller , George Katopis , Erich Klink , Thomas-Michael Winkel
IPC分类号： H01R13/15
CPC分类号： H05K1/11 , H01R12/523 , H01R13/6466 , H01R13/6471 , H01R13/6589 , H01R13/6625 , H05K1/0216 , H05K1/162 , H05K3/429 , H05K2201/044 , H05K2201/09309 , H05K2201/09336 , H05K2201/10189
摘要： The present invention relates to computer hardware design, and in particular to a printed circuit board (card) comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In particular at locations, where the pins of a card-to-card connector enter the layer structure of the card discontinuities brake the high frequency signal return path of a given signal wiring. In order to close the signal return path around a signal path from card to card including the connector, and thus to limit the signal coupling while concurrently keeping the card design as simple as possible, it is proposed to provide a) an additional capacitance for a given signal wiring in a discontinuity section, b) wherein the additional capacitance is formed by a voltage island placed within a signal layer located next to the given signal wiring.
摘要翻译： 本发明涉及计算机硬件设计，特别涉及一种包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板组件的布线的印刷电路板（卡）。 特别是在卡到卡连接器的引脚进入卡不连续的层结构的位置处，制动给定信号布线的高频信号返回路径。 为了封闭从包括连接器的卡到卡的信号路径周围的信号返回路径，并且因此限制信号耦合，同时保持卡设计尽可能简单，建议提供a）附加电容 在不连续部分中的给定信号布线，b）其中附加电容由放置在位于给定信号布线旁边的信号层内的电压岛形成。
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公开(公告)号：US06437252B1
公开(公告)日：2002-08-20
申请号：US09741455
申请日：2000-12-19
申请人： Simone Rehm , Roland Frech , Erich Klink , Helmut Virag , Thomas-Michael Winkel , Wiren Becker , Bruce Chamberlin , Wai Ma
发明人： Simone Rehm , Roland Frech , Erich Klink , Helmut Virag , Thomas-Michael Winkel , Wiren Becker , Bruce Chamberlin , Wai Ma
IPC分类号： H05K102
摘要： Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.
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公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译： 一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。 为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案 最小化每个活动单位设备当定期运行时的当前需求。 选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动 在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。
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公开(公告)号：US20070109726A1
公开(公告)日：2007-05-17
申请号：US11281688
申请日：2005-11-17
申请人： Wiren Becker , Bruce Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
发明人： Wiren Becker , Bruce Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
IPC分类号： H02B1/00
CPC分类号： H05K1/0262 , H05K1/0298 , H05K1/141 , H05K2201/093 , H05K2201/09327 , H05K2201/09663
摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.
摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。
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公开(公告)号：US08222535B2
公开(公告)日：2012-07-17
申请号：US12169778
申请日：2008-07-09
申请人： Roland Frech , Thomas-Michael Winkel , Erich Klink
发明人： Roland Frech , Thomas-Michael Winkel , Erich Klink
CPC分类号： H04L7/0008 , G06F1/10 , G06F1/14 , H04L7/0037
摘要： A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.
摘要翻译： 一种电路装置，包括一组信号层，一组第一功率层，一组第二功率层，一组信号通路，一组第一功率通孔，一组第二电源通孔，其中， 一组信号通孔提供用于高频（HF）信号电流的信号路径，其中至少一组第一电源通孔的功率通孔和至少一组第二电源通孔的功率通路提供用于返回的返回路径 与信号电流相关联的电流，其中由所述一组第二电力通路的电力通路提供的返回路径与所述一组第二电力层的功率层连接，其中所述一组第一电力层的至少一个电力层 布置在该组第二功率层的功率层与该组信号层的每个信号层之间。
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公开(公告)号：US20080283285A1
公开(公告)日：2008-11-20
申请号：US12169778
申请日：2008-07-09
申请人： Roland Frech , Thomas-Michael Winkel , Erich Klink
发明人： Roland Frech , Thomas-Michael Winkel , Erich Klink
IPC分类号： H05K1/11
CPC分类号： H04L7/0008 , G06F1/10 , G06F1/14 , H04L7/0037
摘要： A circuit arrangement comprising a set of signal layers, a set of first power layers, a set of second power layers, a set of signal vias, a set of first power vias, a set of second power vias, wherein a signal via of the set of signal vias provides a signal path for a high-frequency (HF) signal current, wherein at least a power via of the set of first power vias and at least a power via of the set of second power vias provide return paths for return currents associated with the signal current, wherein the return path provided by the power via of the set of second power vias is connected with a power layer of the set of second power layers, wherein at least one power layer of the set of first power layers is arranged between the power layer of the set of second power layers and each signal layer of the set of signal layers.
摘要翻译： 一种电路装置，包括一组信号层，一组第一功率层，一组第二功率层，一组信号通路，一组第一功率通孔，一组第二电源通孔，其中， 一组信号通孔提供用于高频（HF）信号电流的信号路径，其中至少一组第一电源通孔的功率通孔和至少一组第二电源通孔的功率通路提供用于返回的返回路径 与信号电流相关联的电流，其中由所述一组第二电力通孔的电力通路提供的返回路径与所述一组第二电力层的功率层连接，其中所述一组第一电力层的至少一个功率层 布置在该组第二功率层的功率层与该组信号层的每个信号层之间。
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公开(公告)号：US07355125B2
公开(公告)日：2008-04-08
申请号：US11281688
申请日：2005-11-17
申请人： Wiren D. Becker , Bruce J. Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
发明人： Wiren D. Becker , Bruce J. Chamberlin , Roland Frech , Andreas Huber , George Katopis , Erich Klink , Andreas Rebmann , Thomas-Michael Winkel
IPC分类号： H05K1/03
CPC分类号： H05K1/0262 , H05K1/0298 , H05K1/141 , H05K2201/093 , H05K2201/09327 , H05K2201/09663
摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.
摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。
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公开(公告)号：US08519720B2
公开(公告)日：2013-08-27
申请号：US13087602
申请日：2011-04-15
IPC分类号： G01R27/28
CPC分类号： G01R27/16 , G01R31/3004
摘要： A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).
摘要翻译： 一种用于确定电子系统内的预定负载位置处的电源阻抗分布（| Z（f）|）的方法。 在负载位置施加重复活动（如调制时钟树信号），并测量由该重复活动引起的局部电源电压（U（t））。 不是测量由重复活动引起的相应的电流消耗（I（t）），而是分析计算电流消耗。 本地电源阻抗曲线（| Z（f）|）被计算为测量的电源电压的频域电压和电流消耗量（| U（f）|，| I（f）|） （U（t））和计算出的电流消耗（I（t））。
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