公开(公告)号：US06859410B2

公开(公告)日：2005-02-22

申请号：US10306888

申请日：2002-11-27

申请人： Roy E. Scheuerlein ,  Matthew P. Crowley

发明人： Roy E. Scheuerlein ,  Matthew P. Crowley

IPC分类号： G11C5/02 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C5/025

摘要： A tree decoder organization particularly useful for a three-dimensional memory array or any array having very small array line pitch is configured to provide a plurality of top-level decode nodes, each of which, when selected, simultaneously selects a block of array lines and couples each array line of a selected block to a respective intermediate node. Each of the top-level decode signals has a range of control which is substantially less than the extent of the intermediate nodes. In some embodiments each selected block includes more than one array line on each of at least two memory layers having array lines which exit to one side of the memory array. As a result, the large layout area requirement to generate each top-level decode node is supported by a contiguous block of array lines of the memory array.

摘要翻译： 特别适用于三维存储器阵列或具有非常小的阵列线间距的任何阵列的树解码器组合被配置为提供多个顶级解码节点，每个顶级解码节点当被选择时同时选择阵列线块，并且 将所选块的每个阵列线耦合到相应的中间节点。 每个顶层解码信号都具有一个大大小于中间节点范围的控制范围。 在一些实施例中，每个所选择的块包括至少两个存储器层中的每一个具有排列到存储器阵列的一侧的阵列线的多于一个阵列线。 结果，生成每个顶层解码节点的大布局面积要求由存储器阵列的连续阵列线支持。

公开(公告)号：US06504753B1

公开(公告)日：2003-01-07

申请号：US09897784

申请日：2001-06-29

申请人： Roy E. Scheuerlein ,  Matthew P. Crowley

发明人： Roy E. Scheuerlein ,  Matthew P. Crowley

IPC分类号： G11C1136

CPC分类号： G11C8/08 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C2207/063

摘要： A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

摘要翻译： 无源元件存储器阵列优选地将所选择的X线偏置到外部接收的VPP电压，并将选定的Y线偏置到地。 未选择的Y线优选地偏置到VPP减去第一偏移电压，并且偏置到第二偏移电压（相对于地）的未选择的X线。 第一和第二偏移电压优选地相同并且具有约0.5至2伏特的值。 VPP电压取决于所使用的存储器单元技术，优选落在5至20伏的范围内。 片上VPP发生器所需的区域，并节省了这种发电机将消耗的功率。 此外，编程操作期间集成电路的工作温度降低，这进一步降低了功耗。 当放电存储器阵列时，层间的电容最好首先放电，然后将这些层放电到地。

公开(公告)号：US07383476B2

公开(公告)日：2008-06-03

申请号：US10774758

申请日：2004-02-09

申请人： Matthew P. Crowley ,  Luca G. Fasoli ,  Alper Ilkbahar ,  Mark G. Johnson ,  Bendik Kleveland ,  Thomas H. Lee ,  Roy E. Scheuerlein

发明人： Matthew P. Crowley ,  Luca G. Fasoli ,  Alper Ilkbahar ,  Mark G. Johnson ,  Bendik Kleveland ,  Thomas H. Lee ,  Roy E. Scheuerlein

IPC分类号： G11C29/00 ,  G11C11/00

CPC分类号： G06F11/1008 ,  G11C7/22 ,  G11C17/00

摘要： In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.

摘要翻译： 在一个实施例中，提供了包括单片三维一次写入存储器阵列和以下系统块中的至少两个的芯片级结构：错误检查和校正电路（ECC）; 包含子数组的棋盘存储器阵列; 写控制器 电荷泵; Vread发生器; 振荡器 带隙参考发生器; 和页面寄存器/故障存储器。 在另一个实施例中，提供了包括单片三维一次写入存储器阵列ECC和智能写入的芯片级架构。 单片三维一次写入存储器阵列包括第一导体，第一导体上方的第一存储单元，第一存储单元上方的第二导体和第二导体上方的第二存储单元，其中第二导体是唯一的 第一和第二存储单元之间的导体。

公开(公告)号：US06856572B2

公开(公告)日：2005-02-15

申请号：US10306887

申请日：2002-11-27

申请人： Roy E. Scheuerlein ,  Matthew P. Crowley

发明人： Roy E. Scheuerlein ,  Matthew P. Crowley

IPC分类号： G11C5/02 ,  G11C8/10 ,  H01L27/06 ,  H01L27/102 ,  G11C8/00

CPC分类号： G11C8/10 ,  G11C5/025 ,  H01L27/0688 ,  H01L27/1021

摘要： A memory array decoder organization readily interfaces to array lines having extremely dense pitch, and in particular interfaces to extremely dense array lines of a three-dimensional memory array. In an exemplary embodiment, a multi-headed decoder includes a group of array line driver circuits associated with a single decode node. Each array line driver circuit couples its associated array line through a first device to an associated upper bias node which is generated to convey either a selected bias condition or an unselected bias condition thereon appropriate for the array line. Each array line driver circuit also couples its associated array line through a second device to an associated lower bias node which is generated to convey an unselected bias condition appropriate for the array line. The array line driver circuits for several different decode nodes may be physically arranged in one or more banks.

摘要翻译： 存储器阵列解码器组织容易地与具有非常密集间距的阵列线接口，并且特别是与三维存储器阵列的非常密集的阵列线的接口。 在示例性实施例中，多头解码器包括与单个解码节点相关联的一组阵列线驱动器电路。 每个阵列线驱动器电路将其相关联的阵列线通过第一器件耦合到相关联的上偏置节点，所述上偏置节点被产生以传送其上适合于阵列线的选定偏置条件或未选择的偏置条件。 每个阵列线驱动电路还将其相关联的阵列线通过第二装置耦合到相关联的下偏置节点，所述下偏置节点被产生以传送适合于阵列线的未选择的偏置条件。 用于多个不同解码节点的阵列线驱动器电路可以物理地布置在一个或多个存储体中。

公开(公告)号：US06661730B1

公开(公告)日：2003-12-09

申请号：US09748649

申请日：2000-12-22

申请人： Roy E. Scheuerlein ,  Matthew P. Crowley

发明人： Roy E. Scheuerlein ,  Matthew P. Crowley

IPC分类号： G11C800

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-array groups. All the associated sub-array groups are preferably selected during a read cycle to simultaneously read the various bits of the data set, but when writing the data set, a smaller number of sub-array groups are activated during each of several write cycles to simultaneously write only a portion of the data set. Consequently, the read bandwidth remains high and is driven by the number of bits simultaneously read, but the write power is reduced since during each write cycle fewer bits are written. Such a memory array is particularly advantageous with passive element memory cells, such as those having antifuses.

摘要翻译： 存储器阵列被细分成许多子阵列，这些子阵列可以分组地选择，每个组包含一个或多个子阵列。 数据集的各种数据位在物理上分散并映射到大量相关联的子阵列组中。 优选地，在读周期期间选择所有相关联的子阵列组以同时读取数据集的各个位，但是当写入数据集时，在几个写周期中的每一个同时激活较少数量的子阵列组 只写一部分数据集。 因此，读取带宽保持高电平并由同时读取的位数驱动，但由于在每个写入周期内写入较少的位，所以写入功率减小。 这种存储器阵列对于诸如具有反熔丝的无源元件存储单元尤为有利。

公开(公告)号：US06633509B2

公开(公告)日：2003-10-14

申请号：US10310225

申请日：2002-12-05

申请人： Roy E. Scheuerlein ,  Matthew P. Crowley

发明人： Roy E. Scheuerlein ,  Matthew P. Crowley

IPC分类号： G11C800

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A memory array is subdivided into many sub-arrays which are separately selectable in groups, with each group containing one or more sub-arrays. The various data bits of a data set are physically spread out and mapped into a large number of associated sub-array groups. All the associated sub-array groups are preferably selected during a read cycle to simultaneously read the various bits of the data set, but when writing the data set, a smaller number of sub-array groups are activated during each of several write cycles to simultaneously write only a portion of the data set. Consequently, the read bandwidth remains high and is driven by the number of bits simultaneously read, but the write power is reduced since during each write cycle fewer bits are written. Such a memory array is particularly advantageous with passive element memory cells, such as those having antifuses.

摘要翻译： 存储器阵列被细分成许多子阵列，这些子阵列可以分组地选择，每个组包含一个或多个子阵列。 数据集的各种数据位在物理上分散并映射到大量相关联的子阵列组中。 优选地，在读周期期间选择所有相关联的子阵列组以同时读取数据集的各个位，但是当写入数据集时，在几个写周期中的每一个同时激活较少数量的子阵列组 只写一部分数据集。 因此，读取带宽保持高电平并由同时读取的位数驱动，但由于在每个写入周期内写入较少的位，所以写入功率减小。 这样的存储器阵列对于无源元件存储单元是特别有利的，例如那些具有反熔丝的存储单元

公开(公告)号：US5991888A

公开(公告)日：1999-11-23

申请号：US938184

申请日：1997-09-26

申请人： Darren R. Faulkner ,  Matthew P. Crowley

发明人： Darren R. Faulkner ,  Matthew P. Crowley

IPC分类号： G01R31/30 ,  G06F1/04 ,  G06F1/08

CPC分类号： G01R31/3016 ,  G06F1/04 ,  G06F1/08

摘要： An electronic system such as a processor or computer system includes circuitry that supports a plurality of clock modes. The clock modes may be used for, for example, testing for critical paths. The clock modes include a variety of clock signal variations that may be utilized such as cycle stretch clock mode, pulse or delay fault mode, and stop mode which provide substantial flexibility in support of a multitude of tests. In one embodiment, a processor of an electronic system includes test clock mode circuitry to support and utilize test clock modes without dependence on an external bypass clock signal operating at processor operational frequencies. Furthermore, the processor implements the test clock modes at full processor operational frequencies. Additionally, a phase-locked loop is utilized to synchronize test mode clock signals with a reference clock signal to, for example, facilitate realistic operational conditions and acquisition of accurate test results. Additionally, in some test clock modes, the phase-locked loop may be synchronized prior to issuing test clock signals to, for example, further support realistic processor operational conditions during, for example, testing operations.

摘要翻译： 诸如处理器或计算机系统的电子系统包括支持多个时钟模式的电路。 时钟模式可用于例如测试关键路径。 时钟模式包括可以使用的各种时钟信号变化，例如周期拉伸时钟模式，脉冲或延迟故障模式以及提供大量灵活性以支持大量测试的停止模式。 在一个实施例中，电子系统的处理器包括测试时钟模式电路，以支持和利用测试时钟模式，而不依赖于在处理器操作频率下操作的外部旁路时钟信号。 此外，处理器在全处理器操作频率下实现测试时钟模式。 此外，使用锁相环来将测试模式时钟信号与参考时钟信号同步，以便例如促进真实的操作条件并获得准确的测试结果。 此外，在一些测试时钟模式中，在发布测试时钟信号之前，锁相环可以被同步，例如在例如测试操作期间进一步支持真实的处理器操作条件。

公开(公告)号：US06947305B2

公开(公告)日：2005-09-20

申请号：US10636036

申请日：2003-08-06

申请人： Matthew P. Crowley

发明人： Matthew P. Crowley

IPC分类号： G11C5/00 ,  H01L21/822 ,  G11C5/06

CPC分类号： H01L27/1021 ,  G11C16/20 ,  G11C2029/1208 ,  H01L21/8221 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/115

摘要： Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photo-lithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

摘要翻译： 从单组光刻掩模制造两种类型的拓扑不同的三​​维集成电路（例如4层三维存储器阵列和8层三维存储器阵列）。 在一个示例中，掩模1-5与其他掩模一起使用以在4层存储器阵列和8层存储器阵列中创建前四级存储器单元。 8层存储器阵列完成了掩模，用于形成阵列的前四层。 集成电路识别电路通过检测跨过集成电路的一些或全部器件电平的导电路径是否连续，然后通过选择适当的电路识别信号来为两种类型的集成电路生成适当的电路识别信号。

公开(公告)号：US6046621A

公开(公告)日：2000-04-04

申请号：US938193

申请日：1997-09-26

申请人： Matthew P. Crowley

发明人： Matthew P. Crowley

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/14 ,  G11C11/418 ,  G11C29/02 ,  G11C29/32 ,  G11C29/50 ,  H03K5/00 ,  H03K5/13 ,  H03K5/151 ,  H03L7/08 ,  H03L7/099 ,  H03L5/00

CPC分类号： G11C29/026 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/14 ,  H03K5/13 ,  H03K5/151 ,  H03L7/08 ,  G11C11/401 ,  G11C11/41 ,  G11C16/04 ,  G11C17/14 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/0995

摘要： A differential signal generator for generating a true/complement output signal pair in response to a single-ended input signal is disclosed. The differential signal generator includes an input stage that generates a true/complement intermediate signal pair in response to the input signal, and first and second inverters that generate the output signal pair in response to the intermediate signal pair. The first and second inverters have dynamic beta ratios that change in response to the input signal. This is accomplished by coupling a transistor in the first inverter to ground and decoupling a transistor in the second inverter from ground when the input signal has a high value, and decoupling the transistor in the first inverter from ground and coupling the transistor in the second inverter to ground when the input signal has a low value. As a result, the output signal pair cross each other at a predetermined cross-point although the intermediate signal pair does not.

摘要翻译： 公开了一种用于响应于单端输入信号产生真/补输出信号对的差分信号发生器。 差分信号发生器包括响应于输入信号产生真/补中间信号对的输入级，以及响应于中间信号对产生输出信号对的第一和第二反相器。 第一和第二逆变器具有响应于输入信号而变化的动态β比率。 这是通过将第一反相器中的晶体管耦合到地，并且当输入信号具有高值时将第二反相器中的晶体管与地耦合并且将第一反相器中的晶体管与地耦合并且将第二反相器中的晶体管耦合 当输入信号具有低值时接地。 结果，虽然中间信号对没有，输出信号对在预定的交叉点彼此交叉。

公开(公告)号：US5898640A

公开(公告)日：1999-04-27

申请号：US938219

申请日：1997-09-26

申请人： Amos Ben-Meir ,  Matthew P. Crowley

发明人： Amos Ben-Meir ,  Matthew P. Crowley

IPC分类号： G11C7/22 ,  H03K5/26 ,  G11C8/00

CPC分类号： G11C7/22 ,  H03K5/26

摘要： An even bus clock circuit generates logic pulses in response to substantially coincident rising edges of a processor clock and a bus clock over a given range of processor clock to bus clock ratios that includes whole integers and half integers. The even bus clock circuit includes a delay element for receiving the bus clock and generating a delayed bus clock, a first flip-flop for receiving the processor clock at a data input and receiving the delayed bus clock at a clock input, and a second flip-flop for receiving a data output of the first flip-flop at a data input, receiving the processor clock at a clock input and generating a data output that is coupled to an asynchronous reset input of the first flip-flop. The logic pulses are generated at the data output of the first flip-flop and have a pulse width of substantially the same duration as a single cycle of the processor clock.

摘要翻译： 偶数总线时钟电路响应于处理器时钟和总线时钟在给定范围的处理器时钟到总线时钟比的基本上一致的上升沿产生逻辑脉冲，其包括整数和整数。 偶数总线时钟电路包括用于接收总线时钟并产生延迟的总线时钟的延迟元件，用于在数据输入处接收处理器时钟并在时钟输入处接收延迟的总线时钟的第一触发器，以及第二触发器 用于在数据输入端接收第一触发器的数据输出，在时钟输入端接收处理器时钟，并产生耦合到第一触发器的异步复位输入的数据输出。 逻辑脉冲在第一触发器的数据输出处产生，并且具有与处理器时钟的单个周期基本相同的持续时间的脉冲宽度。