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14 条记录 (耗时 0.023 秒)

    ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process
    5.
    发明授权
    ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process 失效
    用于0.35μm3.3V 70A栅极氧化工艺的ESD注入方案

    公开(公告)号：US5953601A

    公开(公告)日：1999-09-14

    申请号：US24480

    申请日：1998-02-17

    申请人： Ruey-Yun Shiue ,  Chin-Shan Hou ,  Yi-Hsun Wu ,  Lin-June Wu

    发明人： Ruey-Yun Shiue ,  Chin-Shan Hou ,  Yi-Hsun Wu ,  Lin-June Wu

    IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8236

    CPC分类号： H01L27/0266 ,  H01L21/823814 ,  H01L27/0922

    摘要： A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

    摘要翻译： 公开了一种提高0.35μm技术以下，接近0.25μm的超大规模集成电路中的栅极氧化物的ESD保护的方法。 这通过提供硅衬底并在其上形成产品FET器件电路和ESD保护器件电路来实现。 在形成ESD源极/漏极区域时，注入物质从磷变为硼，从而降低结击穿电压。 离子注入在具有高泄漏和电容的区域中明智地执行。 因此，通过降低击穿电压以及通过减小接合部的泄漏和电容来实现改进。 此外，在接触区域上形成硅化物之前，使用光致抗蚀剂掩模进行离子注入。 这避免了硅化物降解的问题，并且通过在高能量ESD注入期间通过将金属离子输送到结的耗尽区域而引起的接触电阻的伴随增加。

    Bonding pad structure to minimize IMD cracking
    6.
    发明授权
    Bonding pad structure to minimize IMD cracking 有权
    粘合垫结构以最小化IMD开裂

    公开(公告)号：US07759797B2

    公开(公告)日：2010-07-20

    申请号：US11546078

    申请日：2006-10-11

    申请人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    发明人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    IPC分类号： H01L23/528

    CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

    摘要： A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

    摘要翻译： 公开了形成对IMD开裂免疫的接合垫的方法。 提供部分处理半导体晶片，其具有完成了所有金属水平。 在最上层的金属层上形成有覆盖层的介电层。 形成和蚀刻所述电介质层水平和垂直的沟槽阵列形成通过电介质层并将电介质层分离成电池。 沟槽填充有导电材料，并且在执行CMP之后，沉积粘合金属图案。 电线被接合到所述接合金属图案上，之后形成钝化层。

    Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology
    7.
    发明授权
    Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology 有权
    离子混合两步钛沉积工艺的钛硅化物CMOS技术

    公开(公告)号：US06451679B1

    公开(公告)日：2002-09-17

    申请号：US09541480

    申请日：2000-04-03

    申请人： Chu-Wei Hu ,  Jine-Wen Weng ,  Ruey-Yun Shiue

    发明人： Chu-Wei Hu ,  Jine-Wen Weng ,  Ruey-Yun Shiue

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    摘要： A new method of forming selective salicide is described, whereby low resistance salicide is formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without affecting device electrical performance. This invention describes a selective salicide process forming titanium salicide on exposed MOSFET CMOS devices using ion implantation for effective ion mixing between a two-step titanium deposition process. First, a thin layer of titanium is deposited on exposed polysilicon gate and exposed lightly doped source/drain (LLD) regions. Second, a low energy ion implantation of Si+ is performed with peak dose targeted to be just below the Ti/Si interface. Third, an initial rapid thermal anneal (RTA) is performed followed by a selective etch to remove unwanted, excess titanium. The final step is another rapid thermal anneal (RTA) to fully convert the silicide from C49 crystal structure to the preferred C54 structure, for low resistivity. Hence, low resistivity self-aligned silicide is formed on narrow polygates and lightly doped source/drains (LLD) without affecting device electrical performance.

    摘要翻译： 描述了形成选择性自对准硅化物的新方法，由此在暴露的MOSFET CMOS，窄多晶硅栅极和轻掺杂源极/漏极（LLD）上形成低电阻自对准硅化物，而不影响器件电性能。 本发明描述了一种在暴露的MOSFET CMOS器件上使用离子注入形成钛硅化物的选择性自对准硅化物工艺，用于两步钛沉积工艺之间的有效离子混合。 首先，在暴露的多晶硅栅极和暴露的轻掺杂源极/漏极（LLD）区域上沉积薄层的钛。 其次，Si +的低能量离子注入是以峰值剂量为目标，即低于Ti / Si界面。 第三，进行初始快速热退火（RTA），然后进行选择性蚀刻以去除不需要的多余的钛。 最后一步是另一种快速热退火（RTA），以将低硅电解质的硅化物从C49晶体结构完全转化为优选的C54结构。 因此，低电阻率自对准硅化物形成在窄多孔栅极和轻掺杂源极/漏极（LLD）上，而不影响器件电性能。

    Plasma damage monitor
    8.
    发明授权
    Plasma damage monitor 失效
    等离子体损伤监视器

    公开(公告)号：US5781445A

    公开(公告)日：1998-07-14

    申请号：US701361

    申请日：1996-08-22

    申请人： Ruey-Yun Shiue ,  Sung-Mu Hsu

    发明人： Ruey-Yun Shiue ,  Sung-Mu Hsu

    IPC分类号： H01L21/3213 ,  H01L23/544 ,  H01L21/02 ,  H01L21/8249

    CPC分类号： H01L22/34 ,  H01L21/32137 ,  H01L2924/0002

    摘要： A test structure is described which indicates the occurrence of plasma damage resulting from back-end-of-line processing of integrated circuits. The structure consists of a MOSFET which is surrounded by a conductive shield grounded to the substrate silicon along its base perimeter. The walls of the shield are formed from the sundry levels of conductive layers applied during the integrated circuit interconnection metallization beginning with contact metallurgy which is connected to a diffusion within the substrate. This diffusion is formed within a trench in field oxide surrounding the MOSFET and is of the same conductive type as the substrate material. The top conductive plate of the test structure is formed from a selected metallization layer of the integrated circuit. By forming test structures with top conductive plates formed from two different metallization levels, the plasma damage incurred during the intervening processing steps can be uniquely determined. The test structures may be formed within the wafer saw-kerf area or within wafer test sites. Testing is accomplished by measuring shifts in threshold voltage and drive current before and after gate current stressing. Differences in these shifts from one metallization level to another indicate damage in the MOSFETs gate region has occurred during the processing steps which lie between the depositions of the top conductive plates of the two shields.

    摘要翻译： 描述了一种测试结构，其表示由集成电路的后端处理引起的等离子体损伤的发生。 该结构由一个MOSFET组成，该MOSFET由导电屏蔽层围绕，该导电屏蔽层沿其基极周边与衬底硅接地。 屏蔽的壁由在连接到衬底内的扩散的接触冶金开始的集成电路互连金属化期间施加的各种各样的导电层形成。 该扩散形成在围绕MOSFET的场氧化物的沟槽内，并且具有与衬底材料相同的导电类型。 测试结构的顶部导电板由集成电路的选定的金属化层形成。 通过形成具有由两个不同金属化水平形成的顶部导电板的测试结构，可以唯一地确定在中间处理步骤期间产生的等离子体损伤。 测试结构可以形成在晶片锯切区域内或晶片测试位置内。 通过测量门电压应力前后的阈值电压和驱动电流的变化来实现测试。 从一个金属化水平到另一个金属化水平的这些偏移的差异表明，在位于两个屏蔽的顶部导电板的沉积之间的处理步骤期间已经发生MOSFET栅极区域的损坏。

    Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits
    9.
    发明授权
    Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits 失效

    公开(公告)号：US5946567A

    公开(公告)日：1999-08-31

    申请号：US44761

    申请日：1998-03-20

    申请人： Jiue Wen Weng ,  Ruey-Yun Shiue

    发明人： Jiue Wen Weng ,  Ruey-Yun Shiue

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/40

    摘要： A method for making metal capacitors for deep submicrometer processes for integrated circuits is described. The method provides metal capacitors with high capacitance per unit area, low voltage coefficients, and excellent capacitance distribution (uniformity) across the substrate. The method involves depositing a first insulating layer on a substrate having completed semiconductor devices. A first metal layer is deposited and patterned to form bottom electrodes and interconnecting metal lines. A thin capacitor dielectric layer is deposited, and a thin second metal or TiN layer is deposited and patterned to form the top electrodes. A thick second insulating layer is deposited and planarized, and an array of via holes are etched to the top electrodes to provide for low-resistance contacts and via holes for the interconnecting metal lines. A third conducting metal layer is deposited over the second insulating layer and in the via holes, and is patterned to form a thick metal plate over the capacitors to provide low-resistance contacts to the capacitors and concurrently to form the next level of metal interconnections.