公开(公告)号：US12237265B2

公开(公告)日：2025-02-25

申请号：US18321917

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L29/786 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US11778811B2

公开(公告)日：2023-10-03

申请号：US17555829

申请日：2021-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Sang Chui Shin ,  Bong-Soo Kim ,  Jiyoung Kim

IPC: H10B12/00 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B12/482 ,  G11C5/063 ,  H01L21/7682 ,  H01L23/5283 ,  H10B12/02 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/30 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H01L21/76897

Abstract: A semiconductor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

公开(公告)号：US20240272995A1

公开(公告)日：2024-08-15

申请号：US18397764

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangeun LEE ,  Sumin Kim ,  Dongjun Lee

IPC: G06F11/20 ,  G06F13/40

CPC classification number: G06F11/2002 ,  G06F13/4022 ,  G06F2201/85 ,  H04N21/431 ,  H04N21/43635 ,  H04N21/4622 ,  H04N21/485

Abstract: An electronic apparatus includes a display; an input interface including a first high-speed multimedia interface (HDMI) port configured to connect to a first source device, and a second HDMI port configured to connect to a second source device; and at least one processor operatively connected with the display and the input interface, wherein a first switching device is provided in a first consumer electronic control (CEC) line corresponding to the first HDMI port, and a second switching device is provided in a second CEC line corresponding to the second HDMI port, and wherein the at least one processor is configured to: control, based on a malfunction associated with a CEC function being identified from the first source device or the second source device, the display to display a user interface (UI) for turning off the CEC function, and turn off the CEC function by separately controlling at least one of the first switching device or the second switching device based on a user command received through the UI.

公开(公告)号：US20220293420A1

公开(公告)日：2022-09-15

申请号：US17680996

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11270885B2

公开(公告)日：2022-03-08

申请号：US16776948

申请日：2020-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US09931838B2

公开(公告)日：2018-04-03

申请号：US15254019

申请日：2016-09-01

Applicant: SAMSUNG DISPLAY CO., LTD. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjun Lee ,  Minsoo Kim ,  Jongwon Kim ,  Seungdon Lee ,  Hyunjin Lee

IPC: B41J2/045 ,  H01L51/56 ,  H01L51/52 ,  H01L27/32 ,  G02F1/133 ,  G02F1/1337 ,  G02F1/1341

CPC classification number: B41J2/04541 ,  B41J2/04586 ,  G02F1/1303 ,  G02F1/13306 ,  G02F1/1337 ,  G02F1/1341 ,  H01L27/3244 ,  H01L51/0005 ,  H01L51/5253 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/558

Abstract: An inkjet printing method includes: setting a first region to be printed at a constant print density within a target region to be printed; setting a second region within the target region and closer than the first region to an edge of the target region, wherein the second region is to be printed at a print density that varies according to a position; generating control data for a plurality of nozzles provided on an inkjet head in order to print the first region and the second region; and driving the inkjet head according to the control data.

公开(公告)号：US11688687B2

公开(公告)日：2023-06-27

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L21/768 ,  H10B12/00

CPC classification number: H01L23/528 ,  H01L21/76805 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50 ,  H01L21/76807 ,  H10B12/053

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US20220037251A1

公开(公告)日：2022-02-03

申请号：US17198591

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangoh Park ,  Dongjun Lee ,  Keunnam Kim ,  Seunghune Yang

IPC: H01L23/528 ,  H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

公开(公告)号：US11205652B2

公开(公告)日：2021-12-21

申请号：US16506316

申请日：2019-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Sang Chul Shin ,  Bong-Soo Kim ,  Jiyoung Kim

IPC: H01L27/108 ,  G11C5/06 ,  H01L21/768 ,  H01L23/528

Abstract: A semicondcutor memory device may include a substrate, a bit line structure extending in one direction on the substrate, the bit line structure including a sidewall, a storage node contact on the sidewall of the bit line structure, first and second spacers between the sidewall of the bit line structure and the storage node contact, the first spacer separated from the second spacer by a space between the first spacer and the second spacer, an interlayer dielectric layer on the bit line structure, the interlayer dielectric layer including a bottom surface, a spacer capping pattern extending downward from the bottom surface of the interlayer dielectric layer toward the space between the first and second spacers, and a landing pad structure penetrating the interlayer dielectric layer, the landing pad structure coupled to the storage node contact.

公开(公告)号：US11728167B2

公开(公告)日：2023-08-15

申请号：US17680996

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76816

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.