公开(公告)号：US20170076975A1

公开(公告)日：2017-03-16

申请号：US15359724

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20170358545A1

公开(公告)日：2017-12-14

申请号：US15440621

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-IL CHOI ,  HYOJU KIM ,  KWANGJIN MOON ,  SUJEONG PARK ,  JUBIN SEO ,  NAEIN LEE ,  HO-JIN LEE

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US20170323850A1

公开(公告)日：2017-11-09

申请号：US15659125

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/764

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20160247759A1

公开(公告)日：2016-08-25

申请号：US15146112

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20150332955A1

公开(公告)日：2015-11-19

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。