公开(公告)号：US09686870B2

公开(公告)日：2017-06-20

申请号：US14566198

申请日：2014-12-10

申请人： Intel Corporation

发明人： Weng Hong Teh ,  John S. Guzek

IPC分类号： H05K3/32 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC分类号： H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

公开(公告)号：US20160225730A1

公开(公告)日：2016-08-04

申请号：US15094759

申请日：2016-04-08

申请人： Waseda University

发明人： Kohei Tatsumi

IPC分类号： H01L23/00

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/76 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05173 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05673 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13411 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24225 ,  H01L2224/24245 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/29012 ,  H01L2224/29017 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40991 ,  H01L2224/40996 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48873 ,  H01L2224/48991 ,  H01L2224/48996 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/75754 ,  H01L2224/76754 ,  H01L2224/81002 ,  H01L2224/81205 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81473 ,  H01L2224/81815 ,  H01L2224/8184 ,  H01L2224/81901 ,  H01L2224/8192 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82399 ,  H01L2224/83002 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83473 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83901 ,  H01L2224/8392 ,  H01L2224/8492 ,  H01L2224/85205 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/9201 ,  H01L2924/00011 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01045 ,  H01L2224/18 ,  H01L2224/24 ,  H01L2224/82 ,  H01L2224/83205

摘要： An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

摘要翻译： 电极连接结构包括：电路的第一电极; 以及电连接到第一电极的电路的第二电极。 第一和第二电极彼此直接或间接地相对地设置。 通过从接触区域的表面和第一和第二电极的相对表面的电镀工艺基本均匀地形成电镀层叠体。 接触区域表面附近的空隙通过形成电镀层而被填充。 在接触区域以外的区域中由第一电极和第二电极的相对表面形成的电镀层的部分不接合在一起。

公开(公告)号：US20150111343A1

公开(公告)日：2015-04-23

申请号：US14581653

申请日：2014-12-23

申请人： Infineon Technologies AG

发明人： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

摘要： An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

摘要翻译： 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US09601448B2

公开(公告)日：2017-03-21

申请号：US15094759

申请日：2016-04-08

申请人： Waseda University

发明人： Kohei Tatsumi

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L21/52 ,  H01L23/498

CPC分类号： H01L24/10 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/76 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/04 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05173 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05673 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13411 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24225 ,  H01L2224/24245 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/29012 ,  H01L2224/29017 ,  H01L2224/29147 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/40095 ,  H01L2224/40227 ,  H01L2224/40991 ,  H01L2224/40996 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48873 ,  H01L2224/48991 ,  H01L2224/48996 ,  H01L2224/73255 ,  H01L2224/73265 ,  H01L2224/73273 ,  H01L2224/73277 ,  H01L2224/75754 ,  H01L2224/76754 ,  H01L2224/81002 ,  H01L2224/81205 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81473 ,  H01L2224/81815 ,  H01L2224/8184 ,  H01L2224/81901 ,  H01L2224/8192 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82399 ,  H01L2224/83002 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83473 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83901 ,  H01L2224/8392 ,  H01L2224/8492 ,  H01L2224/85205 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/9201 ,  H01L2924/00011 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01045 ,  H01L2224/18 ,  H01L2224/24 ,  H01L2224/82 ,  H01L2224/83205

摘要： An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

公开(公告)号：US09412728B2

公开(公告)日：2016-08-09

申请号：US14418842

申请日：2013-07-19

申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

发明人： Carlotta Guiducci ,  Yusuf Leblebici ,  Yuksel Temiz

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  G03F7/20 ,  G03F7/32

CPC分类号： H01L25/50 ,  G03F7/2022 ,  G03F7/32 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3185 ,  H01L24/02 ,  H01L24/05 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68381 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/27002 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82005 ,  H01L2224/8201 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/82143 ,  H01L2224/83143 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9205 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/00013 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A method for performing a post processing pattern on a diced chip having a footprint, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.

摘要翻译： 一种用于在具有覆盖区的切割芯片上执行后处理图案的方法，包括以下步骤：提供支撑晶片; 将第一干膜光致抗蚀剂施加到所述支撑晶片; 将对应于切割的芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; 将掩模和第一干膜光致抗蚀剂暴露于UV辐射; 取下面具; 光致抗蚀剂显影曝光的第一干膜光致抗蚀剂以获得与切割芯片相对应的空腔; 将切割的芯片定位在腔内; 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; 并且根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂。

公开(公告)号：US20160111408A1

公开(公告)日：2016-04-21

申请号：US14967629

申请日：2015-12-14

申请人： RENSSELAER POLYTECHNIC INSTITUTE

发明人： Robert F. Karlicek, JR. ,  James Jian-Qiang Lu ,  Charles Sanford Goodwin ,  Anton Tkachenko

IPC分类号： H01L25/00 ,  H01L25/075

CPC分类号： H01L25/50 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/76 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0753 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/13101 ,  H01L2224/24225 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/75655 ,  H01L2224/75701 ,  H01L2224/75733 ,  H01L2224/75801 ,  H01L2224/76655 ,  H01L2224/76701 ,  H01L2224/76733 ,  H01L2224/76801 ,  H01L2224/82002 ,  H01L2224/82102 ,  H01L2224/82143 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/8323 ,  H01L2224/83801 ,  H01L2224/9202 ,  H01L2224/95101 ,  H01L2224/95144 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/3511 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/83205 ,  H01L2924/00014

摘要： Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.

公开(公告)号：US20150135526A1

公开(公告)日：2015-05-21

申请号：US14566198

申请日：2014-12-10

申请人： Intel Corporation

发明人： WENG HONG TEH ,  JOHN S. GUZEK

IPC分类号： H05K3/32

CPC分类号： H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

公开(公告)号：US20120326271A1

公开(公告)日：2012-12-27

申请号：US13169162

申请日：2011-06-27

申请人： Weng Hong Teh ,  John S. Guzek

发明人： Weng Hong Teh ,  John S. Guzek

IPC分类号： H01L29/66 ,  H01L21/56 ,  H01R43/00 ,  H01L21/283

CPC分类号： H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

公开(公告)号：US20240363575A1

公开(公告)日：2024-10-31

申请号：US18480897

申请日：2023-10-04

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jihwan KIM ,  Seungwon IM ,  Oseob JEON ,  Hangil SHIN ,  Taekyun KIM

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L25/11

CPC分类号： H01L24/24 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/82 ,  H01L25/072 ,  H01L25/115 ,  H01L23/4924 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82002 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A fan out package may include a plurality of semiconductor dies, each of the semiconductor dies including a first surface and a second surface opposite to the first surface. The fan out package includes a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies, a dieback conductive member coupled to the second surface of each of the plurality of semiconductors dies, and an encapsulation material coupled to the plurality of semiconductor dies and the dieback conductive member.

公开(公告)号：US09245875B2

公开(公告)日：2016-01-26

申请号：US14394501

申请日：2013-04-19

申请人： Rensselaer Polytechnic Institute

发明人： Robert F. Karlicek ,  James Jian-Qiang Lu ,  Charles Sanford Goodwin ,  Anton Tkachenko

IPC分类号： H01L25/075 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L25/50 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/76 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0753 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/13101 ,  H01L2224/24225 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/75655 ,  H01L2224/75701 ,  H01L2224/75733 ,  H01L2224/75801 ,  H01L2224/76655 ,  H01L2224/76701 ,  H01L2224/76733 ,  H01L2224/76801 ,  H01L2224/82002 ,  H01L2224/82102 ,  H01L2224/82143 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/8323 ,  H01L2224/83801 ,  H01L2224/9202 ,  H01L2224/95101 ,  H01L2224/95144 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/3511 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/83205 ,  H01L2924/00014

摘要： Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising: positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.