中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.023 seconds)

    SPUTTERING TARGET AND METHOD FOR FORMING SPUTTERING TARGET
    1.
    发明公开
    SPUTTERING TARGET AND METHOD FOR FORMING SPUTTERING TARGET 审中-公开

    公开(公告)号：US20240002998A1

    公开(公告)日：2024-01-04

    申请号：US18213683

    申请日：2023-06-23

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Yuichi SATO ,  Fumito ISAKA ,  Toshikazu OHNO

    IPC: C23C14/34

    CPC classification number: C23C14/3414

    Abstract: A novel sputtering target is provided. The sputtering target includes a first region and a second region. The first region contains a first metal oxide containing an element M1 (the element M1 is one or more elements selected from Al, Ga, Si, Mg, Zr, and B). The second region contains a second metal oxide containing indium and zinc. The first region and the second region are separated from each other. Each of the first region and the second region is a crystal grain. A crystal grain boundary is observed between the first region and the second region. The diameter of each of the first region and the second region is greater than or equal to 5 nm and less than or equal to 10 μm.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250159900A1

    公开(公告)日：2025-05-15

    申请号：US18839097

    申请日：2023-02-13

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Hitoshi KUNITAKE ,  Fumito ISAKA ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

    IPC: H10B53/30 ,  H10B53/20

    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor that includes a first conductor, a first insulator, a first metal oxide, a second insulator, a second conductor, and a third conductor and a fourth conductor which cover parts of a top surface and parts of a side surface of the first metal oxide, which are stacked in this order from the bottom. A second transistor includes a fifth conductor, the first insulator, a second metal oxide, a third insulator, a sixth conductor, and a seventh conductor and a eighth conductor which cover parts of a top surface and parts of a side surface of the second metal oxide, which are stacked in this order from the bottom. A third transistor includes a ninth conductor, the first insulator, the second metal oxide, a fourth insulator, a tenth conductor, an eighth conductor, and an eleventh conductor covering part of the top surface and part of the side surface of the second metal oxide, which are stacked in this order from the bottom. One electrode of a capacitor including a material that can have ferroelectricity is electrically connected to the third conductor and the sixth conductor.

    OXIDE SEMICONDUCTOR LAYER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
    4.
    发明申请
    OXIDE SEMICONDUCTOR LAYER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250015195A1

    公开(公告)日：2025-01-09

    申请号：US18763192

    申请日：2024-07-03

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Fumito ISAKA ,  Yuichi SATO ,  Toshikazu OHNO ,  Hitoshi KUNITAKE ,  Tsutomu MURAKAWA

    IPC: H01L29/786 ,  H01L29/66

    Abstract: A semiconductor device including an oxide semiconductor layer which is formed over a substrate and includes indium is provided. The oxide semiconductor layer is formed in parallel or substantially in parallel with a surface of the substrate. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a formation surface of the oxide semiconductor layer to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the formation surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the formation surface are observed in each of the first region, the second region, and the third region.

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230397427A1

    公开(公告)日：2023-12-07

    申请号：US18024285

    申请日：2021-09-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Hitoshi KUNITAKE ,  Yuji EGI ,  Fumito ISAKA

    IPC: H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40 ,  H01L29/78 ,  H10B63/10 ,  H10N50/10

    CPC classification number: H10B51/30 ,  H10B51/40 ,  H10B53/30 ,  H10B53/40 ,  H01L29/78391 ,  H10B63/10 ,  H10N50/10

    Abstract: A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element and an input terminal of the second FTJ element. In data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with the data. In data reading, voltage with which the polarization does not change is applied between the output terminal of the first FTJ element and the input terminal of the second FTJ element. At this time, the first transistor is turned on, whereby a differential current between current flowing through the first FTJ element and current flowing through the second FTJ element flows through the first transistor. Obtaining the differential current using a read circuit or the like enables the data written to the first FTJ element and the second FTJ element to be read.

    SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240395940A1

    公开(公告)日：2024-11-28

    申请号：US18664493

    申请日：2024-05-15

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Fumito ISAKA ,  Yuichi SATO ,  Toshikazu OHNO ,  Hitoshi KUNITAKE ,  Tsutomu MURAKAWA

    IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00

    Abstract: A transistor with high electrical characteristics is provided. A transistor with a high on-state current is provided. A transistor with small parasitic capacitance is provided. A transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated is provided. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer over the semiconductor layer, and a gate electrode over the gate insulating layer. A first insulating layer is between the first conductive layer and the second conductive layer. The second conductive layer is over the first insulating layer. The first insulating layer and the second conductive layer include an opening portion reaching the first conductive layer. The semiconductor layer is in contact with a sidewall of the opening portion. The semiconductor layer includes a first oxide layer and a second oxide layer. The first oxide layer includes a first region and a second region. The second oxide layer is between the first region and the second region.

Patent Agency Ranking