公开(公告)号：US11217703B2

公开(公告)日：2022-01-04

申请号：US16905120

申请日：2020-06-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi Toriumi ,  Takashi Hamada ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Ryunosuke Honda ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/51 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L27/146 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/423 ,  H01L21/822

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

公开(公告)号：US10693013B2

公开(公告)日：2020-06-23

申请号：US15091009

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi Toriumi ,  Takashi Hamada ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Ryunosuke Honda ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/51 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L27/146 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/423 ,  H01L21/822

Abstract: A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.

公开(公告)号：US10050060B2

公开(公告)日：2018-08-14

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Yuichi Sato ,  Yuji Asano ,  Tetsunori Maruyama ,  Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/78 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L21/8258

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US09443888B2

公开(公告)日：2016-09-13

申请号：US14461938

申请日：2014-08-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L28/20 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Abstract translation: 通过使用含有氢化合物如硅烷（SiH 4）和氨（NH 3）的气体的等离子体CVD形成的氮化硅层910设置在与用于电阻器354的氧化物半导体层905上并直接接触，并且氮化硅 在用于薄膜晶体管355的氧化物半导体层906上设置层910，氧化硅层909用作阻挡层。 因此，与氧化物半导体层906相比，在氧化物半导体层905中引入更高浓度的氢。结果，使用于电阻器354的氧化物半导体层905的电阻比氧化物半导体层的电阻低 906用于薄膜晶体管355。

公开(公告)号：US09941310B2

公开(公告)日：2018-04-10

申请号：US15285661

申请日：2016-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/24

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L28/20 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

公开(公告)号：US08716061B2

公开(公告)日：2014-05-06

申请号：US13718051

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L21/16

CPC classification number: H01L29/66742 ,  C04B35/58 ,  C04B2235/3284 ,  C04B2235/3286 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

Abstract translation: 在使用氧化物半导体的薄膜晶体管中，在氧化物半导体层和源极和漏极电极层之间设置包含铟，镓，锌，氧和氮的缓冲层。

公开(公告)号：US08597977B2

公开(公告)日：2013-12-03

申请号：US13718051

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L21/16

Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

公开(公告)号：US09704976B2

公开(公告)日：2017-07-11

申请号：US14886759

申请日：2015-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji Asano ,  Junichi Koezuka

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L29/423

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/477 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. The thin film transistor is formed in such a manner that a buffer layer including a high-resistance region and low-resistance regions is formed over an oxide semiconductor layer, and the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the low-resistance region of the buffer layer interposed therebetween.

公开(公告)号：US09419113B2

公开(公告)日：2016-08-16

申请号：US14881578

申请日：2015-10-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji Asano ,  Junichi Koezuka

IPC: H01L21/4763 ,  H01L21/477 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/465 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/465 ,  H01L21/47635 ,  H01L21/477 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained.

Abstract translation: 目的是提供一种使用氧化物半导体层的薄膜晶体管，其中氧化物半导体层和源极和漏极电极层之间的接触电阻减小并且电特性稳定。 另一个目的是提供制造薄膜晶体管的方法。 使用氧化物半导体层的薄膜晶体管形成为在氧化物半导体层上形成具有比氧化物半导体层更高的导电性的缓冲层，在缓冲层上形成源极和漏极层，并且氧化物半导体 层与源极和漏极电极层电连接，缓冲层插入其间。 此外，缓冲层在氮气气氛中进行反溅射处理和热处理，由此获得具有比氧化物半导体层更高的导电性的缓冲层。

公开(公告)号：US10236502B2

公开(公告)日：2019-03-19

申请号：US15625476

申请日：2017-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazutaka Kuriki ,  Mikio Yukawa ,  Yuji Asano

IPC: H01M4/38 ,  H01M12/08 ,  H01M10/0569 ,  H01M4/66 ,  H01M10/0525 ,  H01G11/06 ,  H01G11/28 ,  H01G11/30 ,  H01G11/46 ,  H01G11/50 ,  H01L49/02 ,  H01G11/26 ,  H01M4/04 ,  H01M4/134 ,  H01M4/1395 ,  C30B25/00 ,  C30B29/06 ,  C30B29/62 ,  C30B33/02 ,  H01G11/22 ,  H01G11/68 ,  H01G11/70 ,  H01L21/02 ,  H01M10/0583

Abstract: Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased.