SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20150115223A1

    公开(公告)日:2015-04-30

    申请号:US14526427

    申请日:2014-10-28

    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit. The semiconductor device includes the V-pits having a large size and a high density to efficiently preventing damage to the semiconductor device due to electrostatic discharge.

    Abstract translation: 公开了半导体器件及其制造方法。 半导体器件包括:第一导电型半导体层,包括第一下导电型半导体层和第一上导电型半导体层; 通过所述第一上导电型半导体层的至少一部分的V凹坑; 放置在所述第一导电型半导体上并填充所述V坑的第二导电型半导体层; 以及插入在第一和第二导电类型半导体层之间的有源层,其中V坑穿过有源层。 第一上导电型半导体层具有比第一下导电型半导体层更高的缺陷密度,并且包括包含V坑的起点的V坑生成层。 半导体器件包括具有大尺寸和高密度的V型凹坑,以有效地防止由于静电放电对半导体器件的损坏。

    Single chip multi band LED
    2.
    发明授权

    公开(公告)号:US11557695B2

    公开(公告)日:2023-01-17

    申请号:US17165177

    申请日:2021-02-02

    Abstract: A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer located over the n-type nitride semiconductor layer and having a V-pit, an active layer located on the V-pit generation layer, and a p-type nitride semiconductor layer located on the active layer. The active layer includes a well layer, which includes a first well layer portion formed along a flat surface of the V-pit generation layer and a second well layer portion formed in the V-pit of the V-pit generation layer. The light emitting diode emits light having at least two peak wavelengths at a single chip level.

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US09287367B2

    公开(公告)日:2016-03-15

    申请号:US14526427

    申请日:2014-10-28

    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit. The semiconductor device includes the V-pits having a large size and a high density to efficiently preventing damage to the semiconductor device due to electrostatic discharge.

    Abstract translation: 公开了半导体器件及其制造方法。 半导体器件包括:第一导电型半导体层,包括第一下导电型半导体层和第一上导电型半导体层; 通过所述第一上导电型半导体层的至少一部分的V凹坑; 放置在所述第一导电型半导体上并填充所述V坑的第二导电型半导体层; 以及插入在第一和第二导电类型半导体层之间的有源层,其中V坑穿过有源层。 第一上导电型半导体层具有比第一下导电型半导体层更高的缺陷密度,并且包括包含V坑的起点的V坑生成层。 半导体器件包括具有大尺寸和高密度的V型凹坑,以有效地防止由于静电放电对半导体器件的损坏。

    Light emitting device and manufacturing method thereof

    公开(公告)号:US12176458B2

    公开(公告)日:2024-12-24

    申请号:US18200356

    申请日:2023-05-22

    Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.

    Single chip multi band LED
    5.
    发明授权

    公开(公告)号:US12125945B2

    公开(公告)日:2024-10-22

    申请号:US18097319

    申请日:2023-01-16

    CPC classification number: H01L33/24 H01L33/06 H01L33/32

    Abstract: A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer located over the n-type nitride semiconductor layer and having a V-pit, an active layer located on the V-pit generation layer, and a p-type nitride semiconductor layer located on the active layer. The active layer includes a well layer, which includes a first well layer portion formed along a flat surface of the V-pit generation layer and a second well layer portion formed in the V-pit of the V-pit generation layer. The active layer emits light having at least two peak wavelengths at a single chip level.

    Light emitting device and method of fabricating the same

    公开(公告)号:US09799800B2

    公开(公告)日:2017-10-24

    申请号:US14830651

    申请日:2015-08-19

    Abstract: A light emitting device is provided to include an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer disposed between the p-type semiconductor layer and the active layer. The p-type semiconductor layer includes a hole injection layer, a p-type contact layer, and a hole transport layer. The hole transport layer includes a plurality of undoped layers and at least one intermediate doped layer disposed between the undoped layers. At least one of the undoped layers includes a zone in which hole concentration decreases with increasing distance from the hole injection layer or the p-type contact layer, and the intermediate doped layer is disposed to be at least partially overlapped with a region of the hole transport layer, the region having the hole concentration of 62% to 87% of the hole concentration of the p-type contact layer.

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