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    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
    半导体器件和半导体系统，包括它们

    公开(公告)号：US20160372173A1

    公开(公告)日：2016-12-22

    申请号：US14882942

    申请日：2015-10-14

    申请人： SK hynix Inc.

    发明人： Min Chang KIM ,  Chang Hyun KIM ,  Do Yun LEE ,  Jae Jin LEE ,  Hun Sam JUNG

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/12

    CPC分类号： G11C7/222 ,  G11C7/10 ,  G11C7/109 ,  G11C7/1093

    摘要： A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.

    摘要翻译： 半导体器件可以包括缓冲器控制信号生成电路，输入控制信号生成电路和内部数据生成电路。 缓冲器控制信号生成电路可以被配置为产生缓冲器控制信号。 缓冲器控制信号可以与从写入命令信号的时间点经过预定部分的时间点同步地被使能。 输入控制信号生成电路可以被配置为响应于缓冲器控制信号而接收数据选通信号以产生输入控制信号。 内部数据产生电路可以被配置为接收数据信号以产生内部数据。

    PARALLEL TEST DEVICE AND METHOD
    2.
    发明申请
    PARALLEL TEST DEVICE AND METHOD 有权

    公开(公告)号：US20160322118A1

    公开(公告)日：2016-11-03

    申请号：US15207107

    申请日：2016-07-11

    申请人： SK hynix Inc.

    发明人： Min Chang KIM

    IPC分类号： G11C29/40 ,  G11C29/44 ,  G11C29/36

    CPC分类号： G01R31/31716 ,  G01R31/31921 ,  G11C29/16 ,  G11C29/36 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/2602

    摘要： A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

    DATA INPUT CIRCUITS
    3.
    发明申请
    DATA INPUT CIRCUITS 有权
    数据输入电路

    公开(公告)号：US20140056087A1

    公开(公告)日：2014-02-27

    申请号：US13845203

    申请日：2013-03-18

    申请人： SK HYNIX INC.

    发明人： Min Chang KIM

    IPC分类号： G11C7/22

    CPC分类号： G11C7/222 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C29/12015 ,  G11C2207/2272

    摘要： Data input circuits are provided. The data input circuit includes a drive clock signal generator, a data transmitter and a write driver. The drive clock signal generator is configured to shift and delay a final clock signal generated in response to a pulse of a sampled clock signal and configured to generate a drive clock signal in response to the delayed final clock signal. The data transmitter is configured to output input data signals as write input data signals in response to the drive clock signal. The write driver is configured to receive the write input data signals in response to the drive clock signal to drive signals on global lines.

    摘要翻译： 提供数据输入电路。 数据输入电路包括驱动时钟信号发生器，数据发送器和写入驱动器。 驱动时钟信号发生器被配置为移位和延迟响应于采样的时钟信号的脉冲而产生的最终时钟信号，并被配置为响应延迟的最终时钟信号产生驱动时钟信号。 数据发送器被配置为响应于驱动时钟信号将输入数据信号作为写输入数据信号输出。 写驱动器被配置为响应于驱动时钟信号接收写输入数据信号以驱动全局线上的信号。

    DATA I/O CIRCUITS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    DATA I/O CIRCUITS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
    数据I / O电路和包括其的半导体系统

    公开(公告)号：US20170031747A1

    公开(公告)日：2017-02-02

    申请号：US14947126

    申请日：2015-11-20

    申请人： SK hynix Inc.

    发明人： Chang Hyun KIM ,  Min Chang KIM ,  Do Yun LEE ,  Jae Jin LEE ,  Hun Sam JUNG

    IPC分类号： G06F11/07 ,  G11C7/22 ,  G06F13/28 ,  G11C7/10

    CPC分类号： G06F11/0784 ,  G06F11/0745 ,  G06F11/1048 ,  G06F13/28 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1054 ,  G11C7/222 ,  G11C29/52

    摘要： A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.

    摘要翻译： 半导体系统可以包括第一半导体器件和第二半导体器件。 第一半导体器件可以输出外部选通信号和外部数据。 在写入操作期间，第二半导体器件可以与外部选通信号同步地从外部数据提取错误信息，并且在写入操作期间通过输入/输出（I / O）线输出外部数据和错误信息。 第二半导体器件可以利用加载在I / O线上的错误信息来校正内部数据的错误，以便在读取操作期间输出校正的内部数据作为外部数据。

    PARALLEL TEST DEVICE AND METHOD
    7.
    发明申请
    PARALLEL TEST DEVICE AND METHOD 有权
    并行测试设备和方法

    公开(公告)号：US20150012791A1

    公开(公告)日：2015-01-08

    申请号：US14074820

    申请日：2013-11-08

    申请人： SK hynix Inc.

    发明人： Min Chang KIM

    IPC分类号： G01R31/319

    CPC分类号： G01R31/31716 ,  G01R31/31921 ,  G11C29/16 ,  G11C29/36 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/2602

    摘要： A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.

    摘要翻译： 公开了一种并行测试装置和方法，其涉及通过压缩数据执行多位并行测试的技术。 并行测试装置包括：实现数据输入/输出（I / O）操作的焊盘单元; 多个输入缓冲器，其被配置为响应于缓冲器使能信号激活从所述焊盘单元接收的写入数据，并将写入数据输出到全局输入/输出（GIO）线; 多个输出驱动器，被配置为响应于选通脉冲延迟信号激活从全局I / O（GIO）线接收到的读取数据，并将读取的数据输出到焊盘单元; 以及测试控制器，被配置为在测试模式期间激活所述缓冲器使能信号和所述选通延迟信号，使得从所述多个输出驱动器接收到的读取数据被应用于所述多个输入缓冲器，使得所述读取数据被操作为 写数据。

    SEMICONDUCTOR MEMORY APPARATUS
    10.
    发明申请
    SEMICONDUCTOR MEMORY APPARATUS 审中-公开

    公开(公告)号：US20170200481A1

    公开(公告)日：2017-07-13

    申请号：US15181495

    申请日：2016-06-14

    申请人： SK hynix Inc.

    发明人： Min Chang KIM ,  Chang Hyun KIM ,  Do Yun LEE ,  Jae Jin LEE ,  Hun Sam JUNG

    IPC分类号： G11C7/22 ,  G11C7/10

    CPC分类号： G11C29/38 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/22 ,  G11C29/46 ,  G11C29/56012 ,  G11C2029/2602 ,  G11C2029/4002 ,  G11C2029/5602

    摘要： A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.