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公开(公告)号：US20170221545A1
公开(公告)日：2017-08-03
申请号：US15486044
申请日：2017-04-12
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Yong Woo LEE , Jae Jin LEE , Hun Sam JUNG , Hoe Kwon JUNG
IPC: G11C11/406 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC classification number: G11C11/40611 , G06F13/1636 , G11C11/40603 , G11C11/40615 , G11C11/40622 , G11C11/4087 , G11C11/4094 , G11C11/4096 , Y02D10/14
Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
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公开(公告)号：US20170098477A1
公开(公告)日：2017-04-06
申请号：US15047229
申请日：2016-02-18
Applicant: SK hynix Inc.
Inventor： Min Chang KIM , Chang Hyun KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C29/1201 , G11C7/106 , G11C7/1063 , G11C7/1087 , G11C7/109
Abstract: A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.
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公开(公告)号：US20170031747A1
公开(公告)日：2017-02-02
申请号：US14947126
申请日：2015-11-20
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G06F11/0784 , G06F11/0745 , G06F11/1048 , G06F13/28 , G11C5/04 , G11C7/10 , G11C7/1048 , G11C7/1054 , G11C7/222 , G11C29/52
Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.
Abstract translation: 半导体系统可以包括第一半导体器件和第二半导体器件。 第一半导体器件可以输出外部选通信号和外部数据。 在写入操作期间，第二半导体器件可以与外部选通信号同步地从外部数据提取错误信息，并且在写入操作期间通过输入/输出（I / O）线输出外部数据和错误信息。 第二半导体器件可以利用加载在I / O线上的错误信息来校正内部数据的错误，以便在读取操作期间输出校正的内部数据作为外部数据。
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公开(公告)号：US20150012791A1
公开(公告)日：2015-01-08
申请号：US14074820
申请日：2013-11-08
Applicant: SK hynix Inc.
Inventor： Min Chang KIM
IPC: G01R31/319
CPC classification number: G01R31/31716 , G01R31/31921 , G11C29/16 , G11C29/36 , G11C29/40 , G11C29/44 , G11C2029/2602
Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.
Abstract translation: 公开了一种并行测试装置和方法，其涉及通过压缩数据执行多位并行测试的技术。 并行测试装置包括：实现数据输入/输出（I / O）操作的焊盘单元; 多个输入缓冲器，其被配置为响应于缓冲器使能信号激活从所述焊盘单元接收的写入数据，并将写入数据输出到全局输入/输出（GIO）线; 多个输出驱动器，被配置为响应于选通脉冲延迟信号激活从全局I / O（GIO）线接收到的读取数据，并将读取的数据输出到焊盘单元; 以及测试控制器，被配置为在测试模式期间激活所述缓冲器使能信号和所述选通延迟信号，使得从所述多个输出驱动器接收到的读取数据被应用于所述多个输入缓冲器，使得所述读取数据被操作为 写数据。
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公开(公告)号：US20250125795A1
公开(公告)日：2025-04-17
申请号：US18597637
申请日：2024-03-06
Applicant: SK hynix Inc.
Inventor： Soon Chul KWON , Min Chang KIM , Seul Gi KIM , Hong Joo SONG , Ic Su OH
Abstract: A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
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Patent Agency Ranking
公开(公告)号：US20160372173A1
公开(公告)日：2016-12-22
申请号：US14882942
申请日：2015-10-14
Applicant: SK hynix Inc.
Inventor： Min Chang KIM , Chang Hyun KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C7/222 , G11C7/10 , G11C7/109 , G11C7/1093
Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.
Abstract translation: 半导体器件可以包括缓冲器控制信号生成电路，输入控制信号生成电路和内部数据生成电路。 缓冲器控制信号生成电路可以被配置为产生缓冲器控制信号。 缓冲器控制信号可以与从写入命令信号的时间点经过预定部分的时间点同步地被使能。 输入控制信号生成电路可以被配置为响应于缓冲器控制信号而接收数据选通信号以产生输入控制信号。 内部数据产生电路可以被配置为接收数据信号以产生内部数据。
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公开(公告)号：US20160322118A1
公开(公告)日：2016-11-03
申请号：US15207107
申请日：2016-07-11
Applicant: SK hynix Inc.
Inventor： Min Chang KIM
CPC classification number: G01R31/31716 , G01R31/31921 , G11C29/16 , G11C29/36 , G11C29/40 , G11C29/44 , G11C2029/2602
Abstract: A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.
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公开(公告)号：US20140056087A1
公开(公告)日：2014-02-27
申请号：US13845203
申请日：2013-03-18
Applicant: SK HYNIX INC.
Inventor： Min Chang KIM
IPC: G11C7/22
CPC classification number: G11C7/222 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C29/12015 , G11C2207/2272
Abstract: Data input circuits are provided. The data input circuit includes a drive clock signal generator, a data transmitter and a write driver. The drive clock signal generator is configured to shift and delay a final clock signal generated in response to a pulse of a sampled clock signal and configured to generate a drive clock signal in response to the delayed final clock signal. The data transmitter is configured to output input data signals as write input data signals in response to the drive clock signal. The write driver is configured to receive the write input data signals in response to the drive clock signal to drive signals on global lines.
Abstract translation: 提供数据输入电路。 数据输入电路包括驱动时钟信号发生器，数据发送器和写入驱动器。 驱动时钟信号发生器被配置为移位和延迟响应于采样的时钟信号的脉冲而产生的最终时钟信号，并被配置为响应延迟的最终时钟信号产生驱动时钟信号。 数据发送器被配置为响应于驱动时钟信号将输入数据信号作为写输入数据信号输出。 写驱动器被配置为响应于驱动时钟信号接收写输入数据信号以驱动全局线上的信号。
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公开(公告)号：US20180039532A1
公开(公告)日：2018-02-08
申请号：US15785836
申请日：2017-10-17
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G06F11/0784 , G06F11/0745 , G06F11/1048 , G06F13/28 , G11C5/04 , G11C7/10 , G11C7/1048 , G11C7/1054 , G11C7/222 , G11C29/52
Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output an external strobe signal and external data. The second semiconductor device may extract error information from the external data in synchronization with the external strobe signal during a write operation and outputs the external data and the error information through input/output (I/O) lines during the write operation. The second semiconductor device may correct errors of internal data with the error information loaded on the I/O lines to output the corrected internal data as the external data during a read operation.
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公开(公告)号：US20170206940A1
公开(公告)日：2017-07-20
申请号：US15184064
申请日：2016-06-16
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C7/109 , G11C5/06 , G11C7/08 , G11C7/222 , G11C8/06 , G11C8/12 , G11C8/18 , G11C11/4076 , G11C11/419 , G11C29/023
Abstract: A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive signals from the first chip to generate a latch address based on the received signals from the first chip.
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