公开(公告)号：US20240177997A1

公开(公告)日：2024-05-30

申请号：US18244904

申请日：2023-09-11

Applicant: SPTS Technologies Limited

Inventor： Scott Haymore ,  Tony Wilby ,  Steve Burgess

IPC: H01L21/285 ,  C23C14/02 ,  C23C14/34 ,  H01J37/32 ,  H01J37/34 ,  H01L21/02

CPC classification number: H01L21/2855 ,  C23C14/021 ,  C23C14/345 ,  H01J37/32082 ,  H01J37/3464 ,  H01L21/02068 ,  H01J2237/332 ,  H01J2237/335

Abstract: A PVD apparatus can perform a cleaning step and a deposition step on an electrically conductive feature formed on a semiconductor substrate. The semiconductor substrate with the electrically conductive feature thereon can be positioned on the substrate support. A cleaning step can be performed to remove material from the electrically conductive feature predominantly by etching with ions of an inert gas while the target is simultaneously sputtered. A deposition step is performed by applying no RF bias to the substrate support or applying an RF bias which is less than the RF bias applied to the substrate support during the cleaning step and supplying an electrical signal having an associated electrical power to the target. The RF bias, if present, and electrical power are sufficient to deposit an electrically conductive deposition material onto the electrically conductive feature by PVD.

公开(公告)号：US11521840B2

公开(公告)日：2022-12-06

申请号：US15899634

申请日：2018-02-20

Applicant: SPTS Technologies Limited

Inventor： Anthony Wilby ,  Steve Burgess ,  Ian Moncrieff ,  Clive Widdicks ,  Scott Haymore ,  Rhonda Hyndman

IPC: C23C14/35 ,  H01J37/34 ,  B81B3/00 ,  C23C14/50 ,  H01J37/32 ,  H01L21/02 ,  C23C14/34 ,  H01L21/285 ,  H01L21/768

Abstract: A method and apparatus are for controlling stress variation in a material layer formed via pulsed DC physical vapour deposition. The method includes the steps of providing a chamber having a target from which the material layer is formed and a substrate upon which the material layer is formable, and subsequently introducing a gas within the chamber. The method further includes generating a plasma within the chamber and applying a first magnetic field proximate the target to substantially localise the plasma adjacent the target. An RF bias is applied to the substrate to attract gas ions from the plasma toward the substrate and a second magnetic field is applied proximate the substrate to steer gas ions from the plasma to selective regions upon the material layer formed on the substrate.

公开(公告)号：US11251037B2

公开(公告)日：2022-02-15

申请号：US16541615

申请日：2019-08-15

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Kathrine Crook ,  Steve Burgess

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/505 ,  H01J37/32 ,  C23C16/52

Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.

公开(公告)号：US20210005439A1

公开(公告)日：2021-01-07

申请号：US16918202

申请日：2020-07-01

Applicant: SPTS Technologies Limited

Inventor： Rhonda Hyndman ,  Steve Burgess

IPC: H01J37/34 ,  C23C14/50 ,  C23C14/35

Abstract: A magnetron sputtering apparatus for depositing material onto a substrate, comprises: a chamber comprising a substrate support and a target; a plasma production device configured to produce a plasma within the chamber suitable for sputtering material from the target onto the substrate; and a thermally conductive grid comprising a plurality of cells. Each cell comprises an aperture and the ratio of the height of the cells to the width of the apertures is less than 1.0. The grid is disposed between the substrate support and the target and is substantially parallel to the target. The upper surface of the substrate support is positioned at a distance of 75 mm or less from the lower surface of the target.

公开(公告)号：US10812035B2

公开(公告)日：2020-10-20

申请号：US16129346

申请日：2018-09-12

Applicant: SPTS Technologies Limited

Inventor： Rhonda Hyndman ,  Steve Burgess

IPC: H03H3/10 ,  H03H9/25 ,  C23C14/08 ,  C23C14/34 ,  C23C14/35 ,  H03H9/02 ,  H03H9/145 ,  H03H9/64 ,  H01L41/053 ,  H01L41/23 ,  C23C14/10 ,  C23C14/54 ,  H03H3/08 ,  C23C14/00 ,  H03H3/04

Abstract: A method of reducing non-uniformity in the resonance frequencies of a surface acoustic wave (SAW) device, the SAW device comprising a silicon oxide layer comprising an oxide of silicon deposited over interdigital transducers on a piezoelectric substrate by reactive sputtering. The method comprises positioning a piezoelectric substrate having interdigital transducers on a substrate support, then depositing a silicon oxide layer comprising an oxide of silicon over the piezoelectric substrate and the interdigital transducers to form a SAW device. The substrate support is positioned relative to a sputtering target so that the silicon oxide layer of the SAW device has an arithmetic mean surface roughness (Ra) of 11 angstroms or less.

公开(公告)号：US20200058498A1

公开(公告)日：2020-02-20

申请号：US16541615

申请日：2019-08-15

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Katherine Crook ,  Steve Burgess

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/505 ,  C23C16/34

Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.

公开(公告)号：US12207556B2

公开(公告)日：2025-01-21

申请号：US16865227

申请日：2020-05-01

Applicant: SPTS Technologies Limited

Inventor： Adrian Thomas ,  Steve Burgess ,  Amit Rastogi ,  Tony Wilby ,  Scott Haymore

IPC: H03H3/08 ,  C01B21/06 ,  C23C14/00 ,  C23C14/02 ,  C23C14/06 ,  H03H3/02 ,  H03H9/02 ,  H03H9/17 ,  H10N30/045 ,  H10N30/076 ,  H10N30/082

Abstract: In a method for sputter depositing an additive-containing aluminium nitride film containing an additive element like Sc or Y, a first layer of the additive-containing aluminium nitride film is deposited onto a substrate disposed within a chamber by pulsed DC reactive sputtering. A second layer of the additive-containing aluminium nitride film is deposited onto the first layer by pulsed DC reactive sputtering. The second layer has the same composition as the first layer. A gas or gaseous mixture is introduced into the chamber when depositing the first layer. A gaseous mixture comprising nitrogen gas and an inert gas is introduced into the chamber when depositing the second layer. The percentage of nitrogen gas in the flow rate (in sccm) when depositing the first layer is greater than that when depositing the second layer.

公开(公告)号：US11361975B2

公开(公告)日：2022-06-14

申请号：US16601358

申请日：2019-10-14

Applicant: SPTS Technologies Limited

Inventor： Tony Wilby ,  Steve Burgess

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of fabricating an integrated circuit is disclosed. The method of removing excess metal of a metal interconnection layer during integrated circuit fabrication process comprises the steps of: plasma etching an excess metal portion of the metal interconnection layer using plasma comprising a noble gas, for an etch duration. The method further comprises stopping the etch process prior to the excess metal portion being completely removed and thus prior to a dielectric surface upon which the metal interconnection is formed, becoming completely exposed. The remaining excess metal portion comprising excess metal residues is subsequently removed using a second etch step.

公开(公告)号：US11008651B2

公开(公告)日：2021-05-18

申请号：US15478283

申请日：2017-04-04

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Scott Haymore ,  Amit Rastogi ,  Rhonda Hyndman ,  Steve Burgess ,  Ian Moncrieff ,  Chris Kendal

IPC: C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  C23C14/50 ,  C23C14/54 ,  H01J37/32 ,  H01J37/34

Abstract: A DC magnetron sputtering apparatus is for depositing a film on a substrate. The apparatus includes a chamber, a substrate support positioned within the chamber, a DC magnetron, and an electrical signal supply device for supplying an electrical bias signal that, in use, causes ions to bombard a substrate positioned on the substrate support. The substrate support includes a central region surrounded by an edge region, the central region being raised with respect to the edge region.

公开(公告)号：US10978291B2

公开(公告)日：2021-04-13

申请号：US14483926

申请日：2014-09-11

Applicant: SPTS TECHNOLOGIES LIMITED

Inventor： Alex Theodosiou ,  Steve Burgess

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/67 ,  H01J37/32

Abstract: The invention relates to a method of pre-cleaning a semiconductor structure and to associated modular semiconductor process tools. The method includes the steps of: (i) providing a semiconductor structure having an exposed dielectric layer of an organic dielectric material, wherein the dielectric layer has one or more features formed therein which expose one or more electrically conductive structures to be pre-cleaned, in which the electrically conductive structures each include a metal layer, optionally with a barrier layer formed thereon, and the surface area of the exposed dielectric layer is greater than the surface area of the electrically conductive structures exposed by the dielectric layer; and (ii) pre-cleaning the semiconductor structure by performing an Ar/H2 sputter etch to remove material from the exposed electrically conductive structures and to remove organic dielectric material from the exposed dielectric layer.