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公开(公告)号：US11251478B2
公开(公告)日：2022-02-15
申请号：US16372604
申请日：2019-04-02
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
IPC: H01M2/02 , H01M6/40 , H01M10/04 , H01M2/30 , H01M2/22 , H01M50/10 , H01M50/116 , H01M50/124 , H01M50/528 , H01M50/543
Abstract: An electronic device includes a base substrate, and a plurality of battery substrates constructed from mica and being attached to the base substrate. An aggregate area of the base substrate is greater than an aggregate area of the plurality of battery substrates. The electronic device also includes a plurality of active battery layers, each active battery layer being attached to a different respective battery substrate, with each active battery layer having a smaller area than its corresponding battery substrate. A film is disposed over the plurality of active battery layers and sized such that the film extends beyond each active battery layer to contact each battery substrate, and such that the film extends beyond each battery substrate to contact the base substrate.
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公开(公告)号：US10290838B2
公开(公告)日：2019-05-14
申请号：US14847137
申请日：2015-09-08
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.
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3.发明申请公开(公告)号：US20130178017A1
公开(公告)日：2013-07-11
申请号：US13783529
申请日：2013-03-04
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry , Patrick Hougron , Dominique Touzet , José Mendez
IPC: H01L21/683 , H01L21/78
CPC classification number: H01L21/683 , H01L21/67132 , H01L21/78 , Y10T29/41 , Y10T83/02 , Y10T225/393
Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
Abstract translation: 一种用于从半导体晶片制造半导体芯片的方法，包括以下步骤：在第一支撑框架上紧固外部尺寸小于第一框架的外部尺寸并大于第一框架的内部尺寸的第二支撑框架 ; 将晶片布置在在第二框架上延伸的膜的表面上; 通过使用能够接收第一帧的设备进行晶片处理操作; 将第二框架与第一框架分离并移除第一框架; 并通过使用能够接收第二帧的设备进行晶片处理操作。
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公开(公告)号：US08785297B2
公开(公告)日：2014-07-22
申请号：US13649797
申请日：2012-10-11
Applicant: STMicroelectronics (Tours) SAS
Inventor： Marc Feron , Vincent Jarry , Laurent Barreau
IPC: H01L21/30
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/3114 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/01087
Abstract: A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.
Abstract translation: 一种封装电子部件的方法，包括以下步骤：在半导体晶片的第一表面中形成电子部件; 在第一表面上形成包括由绝缘材料分隔开的导电轨道和通孔的互连堆叠; 在互连堆叠上形成第一和第二接合焊盘; 至少在轮廓上除外，使晶片变薄; 用第一树脂层填充薄的区域; 在所述第一接合焊盘上布置至少一个第一芯片，并在所述第二焊盘上形成焊料凸块; 沉积覆盖第一芯片并部分覆盖焊料凸块的第二树脂层; 将粘合带粘合在第一树脂层上; 并将结构划分成单个芯片。
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公开(公告)号：US08772134B2
公开(公告)日：2014-07-08
申请号：US13783529
申请日：2013-03-04
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry , Patrick Hougron , Dominique Touzet , José Mendez
CPC classification number: H01L21/683 , H01L21/67132 , H01L21/78 , Y10T29/41 , Y10T83/02 , Y10T225/393
Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.
Abstract translation: 一种用于从半导体晶片制造半导体芯片的方法，包括以下步骤：在第一支撑框架上紧固外部尺寸小于第一框架的外部尺寸并大于第一框架的内部尺寸的第二支撑框架 ; 将晶片布置在在第二框架上延伸的膜的表面上; 通过使用能够接收第一帧的设备进行晶片处理操作; 将第二框架与第一框架分离并移除第一框架; 并通过使用能够接收第二帧的设备进行晶片处理操作。
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Patent Agency Ranking
公开(公告)号：US20130216904A1
公开(公告)日：2013-08-22
申请号：US13765255
申请日：2013-02-12
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor： Vincent Jarry
CPC classification number: H01M6/40 , H01M2/0404 , H01M2/0469 , H01M2/30 , H01M6/00 , H01M10/02 , H01M10/0436 , H01M10/0585 , Y10T29/49108 , Y10T29/49114 , Y10T29/49115
Abstract: A method for forming a microbattery including, on a surface of a first substrate, one active battery element and two contact pads, this method including the steps of: a) forming, on a surface of a second substrate, two contact pads with a spacing compatible with the spacing of the pads of the first substrate; and b) arranging the first substrate on the second substrate so that the surfaces face each other and that the pads of the first substrate at least partially superpose to those of the second substrate, where a portion of the pads of the second substrate is not covered by the first substrate.
Abstract translation: 一种形成微电池的方法，包括在第一衬底的表面上具有一个有源电池元件和两个接触焊盘，该方法包括以下步骤：a）在第二衬底的表面上形成两个具有间隔的接触焊盘 与第一衬底的焊盘的间隔相适应; 以及b）将所述第一基板布置在所述第二基板上，使得所述表面彼此面对，并且所述第一基板的所述焊盘至少部分地与所述第二基板的所述焊盘重叠，其中所述第二基板的一部分焊盘不被覆盖 通过第一衬底。
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公开(公告)号：US11575172B2
公开(公告)日：2023-02-07
申请号：US17569016
申请日：2022-01-05
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
IPC: H01M50/116 , H01M50/124 , H01M6/40 , H01M50/10 , H01M10/04 , H01M50/528 , H01M50/543
Abstract: An electronic device includes a base substrate with a mica substrate thereon. A top face of the mica substrate has a surface area smaller than a surface area of a top face of the base substrate. An active battery layer is on the mica substrate and has a top face with a surface area smaller than a surface area of a top face of the mica substrate. An adhesive layer is over the active battery layer, mica substrate, and base substrate. An aluminum film layer is over the adhesive layer, and an insulating polyethylene terephthalate (PET) layer is over the aluminum film layer. A battery pad is on the mica substrate adjacent the active battery layer, and a conductive via extends to the battery pad. A conductive pad is connected to the conductive via. The adhesive, aluminum film, and PET have a hole defined therein exposing the conductive pad.
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公开(公告)号：US20170069883A1
公开(公告)日：2017-03-09
申请号：US14847137
申请日：2015-09-08
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
CPC classification number: H01M2/0207 , H01M2/026 , H01M2/0277 , H01M2/0285 , H01M2/0287 , H01M2/22 , H01M2/30 , H01M6/40 , H01M10/0436 , H01M10/0463 , H01M2220/30
Abstract: A battery encapsulation method includes disposing an active battery layer on each of a plurality of battery substrates, with each battery substrate having a greater area than its corresponding active battery layer. The plurality of battery substrates are attached to an interposer having a greater area than an aggregate area of the plurality of battery substrates. The active battery layers are environmentally sealed by disposing a film over the active battery layers sized such that the film extends beyond the active battery layers to contact the battery substrates and the interposer. The interposer is physically along locations where the film contacts the interposer so as to form a plurality of battery units, with each battery unit including one of the battery substrates with the associated active battery layer disposed thereon and being environmentally sealed by the film.
Abstract translation: 电池封装方法包括在多个电池基板中的每一个上设置有源电池层，其中每个电池基板具有比其相应的有源电池层更大的面积。 多个电池基板被附接到具有比多个电池基板的集合区域更大的面积的插入件。 活性电池层通过在活性电池层上设置薄膜来进行环境密封，活性电池层的尺寸使得膜延伸超过有源电池层以接触电池基板和插入件。 内插器在物理上沿着膜接触插入件的位置，以便形成多个电池单元，每个电池单元包括其中一个电池基板，其中相关联的有源电池层设置在该电池基板上，并被该膜环境密封。
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公开(公告)号：US09356310B2
公开(公告)日：2016-05-31
申请号：US13765255
申请日：2013-02-12
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry
CPC classification number: H01M6/40 , H01M2/0404 , H01M2/0469 , H01M2/30 , H01M6/00 , H01M10/02 , H01M10/0436 , H01M10/0585 , Y10T29/49108 , Y10T29/49114 , Y10T29/49115
Abstract: A method for forming a microbattery including, on a surface of a first substrate, one active battery element and two contact pads, this method including the steps of: a) forming, on a surface of a second substrate, two contact pads with a spacing compatible with the spacing of the pads of the first substrate; and b) arranging the first substrate on the second substrate so that the surfaces face each other and that the pads of the first substrate at least partially superpose to those of the second substrate, where a portion of the pads of the second substrate is not covered by the first substrate.
Abstract translation: 一种形成微电池的方法，包括在第一衬底的表面上具有一个有源电池元件和两个接触焊盘，该方法包括以下步骤：a）在第二衬底的表面上形成两个具有间隔的接触焊盘 与第一衬底的焊盘的间隔相适应; 以及b）将所述第一基板布置在所述第二基板上，使得所述表面彼此面对，并且所述第一基板的所述焊盘至少部分地与所述第二基板的所述焊盘重叠，其中所述第二基板的一部分焊盘不被覆盖 通过第一衬底。
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公开(公告)号：US20130192435A1
公开(公告)日：2013-08-01
申请号：US13754660
申请日：2013-01-30
Applicant: STMicroelectronics (Tours) SAS
Inventor： Vincent Jarry , Philippe Prunet , Thierry Feuillette
IPC: H01L21/463 , B28D5/04
CPC classification number: H01L21/463 , B28D5/042 , H01L21/67092 , Y10T83/0429 , Y10T83/343
Abstract: A device for cutting a wafer provided with grooves on its upper surface having its lower surface supported by a flexible film secured to a frame. This device includes a system for locating the grooves and for positioning the frame with respect to a cutting system, and setting means for positioning the wafer in front of the locating system so that the located area is at a determined distance from the locating system.
Abstract translation: 一种用于切割在其上表面上设置有凹槽的晶片的装置，其具有由固定到框架的柔性膜支撑的下表面。 该装置包括用于定位凹槽并相对于切割系统定位框架的系统，以及用于将晶片定位在定位系统前面的定位装置，使得定位区域距离定位系统确定的距离。
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