公开(公告)号：US20170294370A1

公开(公告)日：2017-10-12

申请号：US15631579

申请日：2017-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4821 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

公开(公告)号：US09640464B2

公开(公告)日：2017-05-02

申请号：US15235373

申请日：2016-08-12

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L21/44 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L21/288 ,  H01L21/3105 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/2885 ,  H01L21/3105 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.

公开(公告)号：US10535535B2

公开(公告)日：2020-01-14

申请号：US16020757

申请日：2018-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.

公开(公告)号：US11018078B2

公开(公告)日：2021-05-25

申请号：US16031998

申请日：2018-07-10

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US10074596B2

公开(公告)日：2018-09-11

申请号：US14969481

申请日：2015-12-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio Marchisi

IPC: H01L21/00 ,  H01L23/495 ,  H05K7/18 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49537 ,  H01L21/4821 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of electrically conductive material. The lead frame is produced by an additive process of conductive material, e.g., by 3D printing, by forming a three-dimensional structure of leads having overlapping surfaces with a gap therebetween.

公开(公告)号：US20160351477A1

公开(公告)日：2016-12-01

申请号：US15235373

申请日：2016-08-12

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L21/56 ,  H01L25/065 ,  H01L21/3105 ,  H01L21/288 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L21/2885 ,  H01L21/3105 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first semiconductor body that is disposed on a first die pad, a second semiconductor body that is disposed on a second die pad, and a plurality of terminal regions that is disposed between the first and second die pads. The first partial cut forms a recess by removing a portion of each of the terminal regions. The recess is defined by a transverse wall, a first sidewall, and a second sidewall. The first and second sidewalls and the transverse wall are coated with an anti-oxidation layer. A second partial cut is made from the top, where the second partial cut removes the transverse wall, separates the first and second semiconductor bodies, and has a width that is greater than a width of the first partial cut.

Abstract translation: 一种表面贴装电子器件的制造方法，包括从组件的底部进行第一部分切割，所述组件的底部包括设置在第一管芯焊盘上的第一半导体本体，设置在第二管芯焊盘上的第二半导体本体， 以及设置在第一和第二管芯焊盘之间的多个端子区域。 第一部分切口通过去除每个端子区域的一部分而形成凹部。 凹部由横向壁，第一侧壁和第二侧壁限定。 第一和第二侧壁和横向壁被涂覆有抗氧化层。 第二部分切割由顶部制成，其中第二部分切口移除横向壁，分离第一和第二半导体本体，并且具有大于第一部分切割宽度的宽度。

公开(公告)号：US11935818B2

公开(公告)日：2024-03-19

申请号：US17328933

申请日：2021-05-24

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/4889 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/3107 ,  H01L24/45 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/85455 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/20755

Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.

公开(公告)号：US09997438B2

公开(公告)日：2018-06-12

申请号：US15631579

申请日：2017-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L21/00 ,  H05K7/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49537 ,  H01L21/4821 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

公开(公告)号：US20160172275A1

公开(公告)日：2016-06-16

申请号：US14840663

申请日：2015-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Marchisi

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/2885 ,  H01L21/3105 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A surface-mount electronic device includes a body of semiconductor material, a lead frame, which forms a plurality of contact terminals, and a package dielectric region, which overlies the semiconductor body. Each contact terminal includes an inner portion that is overlaid by the package dielectric region and an outer portion, which projects laterally beyond the package dielectric region and is delimited by a first lateral surface. The device further includes, for each contact terminal, an anti-oxidation layer, which is disposed on the corresponding first lateral surface.

Abstract translation: 表面贴装电子器件包括半导体材料体，形成多个接触端子的引线框架和覆盖半导体本体的封装电介质区域。 每个接触端子包括由封装电介质区域覆盖的内部部分和横向突出于封装电介质区域并由第一侧表面限定的外部部分。 对于每个接触端子，该装置还包括设置在相应的第一侧​​面上的抗氧化层。