公开(公告)号：US07435659B2

公开(公告)日：2008-10-14

申请号：US11068117

申请日：2005-02-28

申请人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Joseph M. Ramirez

发明人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Joseph M. Ramirez

IPC分类号： H01L21/76

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/2652 ,  H01L21/823493 ,  H01L21/8249 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

摘要翻译： 本发明提供一种具有对准特征的半导体器件的制造方法。 除了其他步骤之外，制造半导体器件的方法可以包括将n型掺杂剂注入衬底中，从而在衬底中形成注入区域和未被注入的区域。 该方法可以进一步包括使用湿式氧化法，湿法氧化法和n型掺杂剂使得注入区域与未被注入的区域的氧化比例为2:1或更大，然后除去氧化部分 从而在植入区域附近留下对准特征。

公开(公告)号：US20080085569A1

公开(公告)日：2008-04-10

申请号：US11531103

申请日：2006-09-12

申请人： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

发明人： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L29/0649 ,  H01L29/8605

摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

摘要翻译： 实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。 为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。 然后可以在夹持电阻器中形成沟槽。 沟槽深度可以通过夹持电阻器的电气测试来确定。 所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实施。 所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

公开(公告)号：US08264038B2

公开(公告)日：2012-09-11

申请号：US12537326

申请日：2009-08-07

申请人： Sameer P. Pendharkar ,  Binghua Hu ,  Xinfen Chen

发明人： Sameer P. Pendharkar ,  Binghua Hu ,  Xinfen Chen

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/73 ,  H01L27/092 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/823892 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7322 ,  H01L29/7816 ,  H01L29/7833

摘要： A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

摘要翻译： 公开了一种掩埋层结构，其包括与连接到IC中的组件的相同导电类型的深阱连接的高电压埋层相邻的浮置掩埋层结构。 浮置掩埋层结构围绕高压掩埋层并且延伸埋层的耗尽区以减小掩埋层的侧边缘处的峰值电场。 当浮动掩埋层结构的尺寸和间距被优化时，连接到掩埋层的阱可被偏压到100伏而不会破坏。 添加围绕第一浮动掩埋层结构的第二浮动掩埋层结构允许埋入层的操作高达140伏。 具有浮动掩埋层结构的掩埋层结构可以并入DEPMOS晶体管，LDMOS晶体管，埋地集电极npn双极晶体管和隔离CMOS电路中。

公开(公告)号：US20080293206A1

公开(公告)日：2008-11-27

申请号：US11753789

申请日：2007-05-25

申请人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

发明人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

摘要翻译： 示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。 具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。 可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。 多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约90或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。 在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

公开(公告)号：US08154101B2

公开(公告)日：2012-04-10

申请号：US12537318

申请日：2009-08-07

申请人： Sameer P. Pendharkar ,  Binghua Hu

发明人： Sameer P. Pendharkar ,  Binghua Hu

IPC分类号： H01L29/861

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/66136

摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

公开(公告)号：US08309423B2

公开(公告)日：2012-11-13

申请号：US13409689

申请日：2012-03-01

申请人： Sameer P. Pendharkar ,  Binghua Hu

发明人： Sameer P. Pendharkar ,  Binghua Hu

IPC分类号： H01L29/861

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L27/0629 ,  H01L29/417 ,  H01L29/66136

摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

摘要翻译： 公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。 重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。 重掺杂的n型区通常连接到阴极下方的n型掩埋层。 重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。 所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

公开(公告)号：US07989232B2

公开(公告)日：2011-08-02

申请号：US11531103

申请日：2006-09-12

申请人： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

发明人： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

IPC分类号： H01L21/66 ,  H01L27/07

CPC分类号： H01L22/12 ,  H01L29/0649 ,  H01L29/8605

摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

摘要翻译： 实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。 为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。 然后可以在夹持电阻器中形成沟槽。 沟槽深度可以通过夹持电阻器的电气测试来确定。 所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实现。 所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

公开(公告)号：US07713825B2

公开(公告)日：2010-05-11

申请号：US11753789

申请日：2007-05-25

申请人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

发明人： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

摘要翻译： 示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。 具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。 可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。 多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约9°或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。 在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

公开(公告)号：US09293357B2

公开(公告)日：2016-03-22

申请号：US13540542

申请日：2012-07-02

申请人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

发明人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

IPC分类号： H01L29/49 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3205

CPC分类号： H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

摘要： The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

摘要翻译： 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US09076760B2

公开(公告)日：2015-07-07

申请号：US13597439

申请日：2012-08-29

申请人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

IPC分类号： G01R31/26 ,  H01L29/417 ,  H01L21/00 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/41725 ,  G06F2101/00 ,  G06F2201/00 ,  H01L21/00 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/808

摘要： A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

摘要翻译： 结型场效应晶体管（JFET）包括具有包括顶侧表面的第一类型半导体表面的衬底和形成在半导体表面中的第二类型的顶栅。 第一型漏极和第一型源形成在顶栅的相对侧上。 第一深沟槽隔离区域具有围绕顶部栅极，漏极和源极的内部第一沟槽壁和外部第一沟槽壁，并且从顶侧表面垂直延伸到深沟槽深度。 形成在半导体表面中的第二类型沉降片在外部第一沟槽壁的外侧横向延伸。 沉降片从顶侧表面垂直延伸到第二类型深部，该深部位于深沟槽深度的下方并且在内部第一沟槽壁的横向内部以提供底部门。