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    Etchant composition and methods of fabricating metal wiring and thin film transistor substrate using the same
    2.
    发明授权
    Etchant composition and methods of fabricating metal wiring and thin film transistor substrate using the same 有权
    蚀刻剂组成和制造金属布线的方法和使用其的薄膜晶体管基板

    公开(公告)号：US09136137B2

    公开(公告)日：2015-09-15

    申请号：US14263956

    申请日：2014-04-28

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： In-Bae Kim ,  Jong-Hyun Choung ,  Youngmin Moon ,  Hongsick Park ,  Gyu-po Kim ,  Won-guk Seo ,  Hyun-cheol Shin ,  Ki-beom Lee ,  Sam-young Cho ,  Seung-yeon Han

    IPC: H01L21/44 ,  H01L21/306 ,  C23F1/18

    CPC classification number: H01L21/30604 ,  C23F1/18 ,  H01L21/32134 ,  H01L27/124 ,  H01L29/45

    Abstract: An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus.

    Abstract translation: 包含0.5重量％至20重量％的过硫酸盐，0.01重量％至1重量％的氟化合物，1重量％至10重量％的无机酸，0.01重量％至2重量％的唑类， 0.1重量％至5重量％的氯化合物，0.05重量％至3重量％的铜盐，0.01重量％至5重量％的抗氧化剂或其盐，基于蚀刻剂的总重量 组合物和水的量足以使蚀刻剂组合物的总重量等于100重量％。 蚀刻剂组合物适用于通过蚀刻包括铜的金属层或制造用于显示装置的薄膜晶体管基板来形成金属布线。

    Display device having input sensor and fabricating method of the input sensor
    4.
    发明授权
    Display device having input sensor and fabricating method of the input sensor 有权

    公开(公告)号：US11600670B2

    公开(公告)日：2023-03-07

    申请号：US17444274

    申请日：2021-08-02

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jong-Hyun Choung ,  Jaeuoon Kim

    IPC: H01L27/32 ,  G06F3/044 ,  G06F3/041

    Abstract: An input sensor of a display device includes: a sensing electrode on a base insulating layer and overlapping a sensing region; and a signal line electrically connected to the sensing electrode and overlapping the non-sensing region, and including: a first conductive layer on the base insulating layer and having a first reflectance, a first conductivity, and a first thickness; a second conductive layer having a second reflectance lower than the first reflectance, a second conductivity lower than the first conductivity, and a second thickness smaller than the first thickness, wherein the second conductive layer is on and in contact with the first conductive layer; and a third conductive layer between the base insulating layer and the first conductive layer, in contact with each of the base insulating layer and the first conductive layer, wherein the third conductive layer contains a material different from that of the second conductive layer.

    Method for manufacturing thin film transistor array panel
    8.
    发明授权
    Method for manufacturing thin film transistor array panel 有权
    制造薄膜晶体管阵列面板的方法

    公开(公告)号：US09490275B2

    公开(公告)日：2016-11-08

    申请号：US14740484

    申请日：2015-06-16

    Applicant: Samsung Display Co., Ltd.

    Inventor： Young Min Moon ,  Jong-Hyun Choung ,  Bong-Kyun Kim

    IPC: H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

    CPC classification number: H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7869

    Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

    Abstract translation: 薄膜晶体管阵列面板包括：基板上的栅极线，并包括栅电极; 所述第一栅极绝缘层在所述基板和所述栅极线上，所述第一栅极绝缘层包括与所述栅极线相邻的第一部分和与所述栅极线重叠并且具有比所述第一部分的厚度小的第二部分; 第一栅极绝缘层上的第二栅极绝缘层; 在所述第二栅极绝缘层上的半导体层; 在半导体层上彼此隔开的源电极和漏电极; 第二栅极绝缘层上的钝化层，源电极和漏电极; 以及钝化层上的像素电极并与漏电极连接。 第一栅极绝缘层和第二栅极绝缘层在彼此相反的方向上具有应力。

    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME 审中-公开
    薄膜晶体管基板及其制造方法

    公开(公告)号：US20160093743A1

    公开(公告)日：2016-03-31

    申请号：US14816767

    申请日：2015-08-03

    Applicant: Samsung Display Co., Ltd.

    Inventor： Bong-Kyun KIM ,  Sang-Won Shin ,  Jong-Hyun Choung

    IPC: H01L29/786 ,  H01L29/24 ,  H01L29/45 ,  H01L27/12 ,  H01L29/423 ,  H01L21/445 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/417

    CPC classification number: H01L29/7869 ,  H01L21/445 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969

    Abstract: A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer partially overlapping the gate electrode, the semiconductor layer including an oxide semiconductor material; a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode and the drain electrode including a barrier layer, a main wiring layer disposed on the barrier layer, and a first capping layer disposed on the main wiring layer and being spaced apart from each other; and second capping layers covering lateral surfaces of the main wiring layers of the source and drain electrodes.

    Abstract translation: 薄膜晶体管基板包括设置在基板上的栅电极; 与所述栅电极部分重叠的半导体层，所述半导体层包括氧化物半导体材料; 设置在所述半导体层上的源电极和漏电极，所述源电极和所述漏极包括阻挡层，设置在所述阻挡层上的主布线层以及设置在所述主布线层上并且间隔开的第一覆盖层 从彼此; 以及覆盖源电极和漏电极的主配线层的侧表面的第二覆盖层。

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