公开(公告)号：US10446575B2

公开(公告)日：2019-10-15

申请号：US16014902

申请日：2018-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Ho Kim ,  Bong-Soon Lim ,  Pan-Suk Kwak ,  Hong-Soo Jeon

IPC: H01L29/76 ,  H01L27/115 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/24 ,  H01L27/1157

Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.

公开(公告)号：US11296066B2

公开(公告)日：2022-04-05

申请号：US16937815

申请日：2020-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Hwa Yun ,  Pan-Suk Kwak ,  Chan-Ho Kim ,  Bong-Soon Lim

IPC: G11C16/04 ,  H01L25/18 ,  G11C16/08 ,  G11C16/24 ,  G11C13/00 ,  H01L25/065 ,  H01L23/00

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

公开(公告)号：US11075216B2

公开(公告)日：2021-07-27

申请号：US16449286

申请日：2019-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Hwa Yun ,  Pan-Suk Kwak ,  Chan-Ho Kim ,  Bong-Soon Lim

IPC: G11C11/00 ,  H01L27/11573 ,  G11C16/08 ,  H01L27/24 ,  G11C16/04 ,  G11C13/00 ,  H01L45/00 ,  G11C11/56 ,  H01L27/11582 ,  G11C7/04 ,  G11C5/02 ,  G11C5/06

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

公开(公告)号：US20190198514A1

公开(公告)日：2019-06-27

申请号：US16108302

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Bum Kim ,  Chan-Ho Kim

IPC: H01L27/11551 ,  H01L27/11578 ,  G11C5/02 ,  G11C16/10 ,  G11C16/34 ,  G11C29/52 ,  G11C29/42

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.

公开(公告)号：US11665907B2

公开(公告)日：2023-05-30

申请号：US17357581

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Hwa Yun ,  Pan-Suk Kwak ,  Chan-Ho Kim ,  Bong-Soon Lim

IPC: G11C11/00 ,  H01L27/11573 ,  G11C16/08 ,  H01L27/24 ,  G11C16/04 ,  G11C13/00 ,  H01L45/00 ,  G11C11/56 ,  H01L27/11582 ,  G11C7/04 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L27/11573 ,  G11C5/025 ,  G11C5/063 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/0028 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/249 ,  H01L45/06 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77 ,  H01L27/2427 ,  H01L45/126 ,  H01L45/144

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

公开(公告)号：US10680005B2

公开(公告)日：2020-06-09

申请号：US16108302

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Bum Kim ,  Chan-Ho Kim

IPC: G11C29/00 ,  H01L27/11551 ,  H01L27/11578 ,  G11C5/02 ,  G11C29/42 ,  G11C16/34 ,  G11C29/52 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/1157 ,  G11C29/04

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.

公开(公告)号：US10361217B2

公开(公告)日：2019-07-23

申请号：US15833342

申请日：2017-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Ho Kim

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L23/528 ,  H01L29/423 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A vertical memory device includes a mold structure and channels. The mold structure includes gate electrodes and insulation patterns arranged on a substrate in which the gate electrodes are disposed at a plurality of levels, respectively, in a vertical direction substantially perpendicular to an upper surface of the substrate. The insulation patterns are disposed between neighboring ones of the gate electrodes. The channels extend through the mold structure in the vertical direction in a hole, and are spaced apart from each other in a horizontal direction substantially parallel to the upper surface of the substrate in the hole. The gate electrodes each includes a plurality of first gate electrodes spaced apart from each other substantially horizontally. The hole extends through one of the first gate electrodes included in each of the gate electrodes. A plurality of channels may be formed in the one hole in the one first gate electrode.

公开(公告)号：US20180182776A1

公开(公告)日：2018-06-28

申请号：US15833342

申请日：2017-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Ho Kim

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/10 ,  H01L23/528 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02647 ,  H01L21/0273 ,  H01L21/28282 ,  H01L21/31144 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7926

Abstract: A vertical memory device includes a mold structure and channels. The mold structure includes gate electrodes and insulation patterns arranged on a substrate in which the gate electrodes are disposed at a plurality of levels, respectively, in a vertical direction substantially perpendicular to an upper surface of the substrate. The insulation patterns are disposed between neighboring ones of the gate electrodes. The channels extend through the mold structure in the vertical direction in a hole, and are spaced apart from each other in a horizontal direction substantially parallel to the upper surface of the substrate in the hole. The gate electrodes each includes a plurality of first gate electrodes spaced apart from each other substantially horizontally. The hole extends through one of the first gate electrodes included in each of the gate electrodes. A plurality of channels may be formed in the one hole in the one first gate electrode.