公开(公告)号：US20150069635A1

公开(公告)日：2015-03-12

申请号：US14463650

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun KIM ,  In-Young LEE ,  Chang-Seong JEON ,  Taeje CHO

IPC: H01L25/10 ,  H01L23/34 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00 ,  H01L23/373

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/345 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/181 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.

Abstract translation: 提供半导体封装及其制造方法。 该方法可以包括在基板上安装包括芯片和传热区域的第一半导体芯片和设置在传热区域上的较低传热图案，将第二半导体芯片安装在第一半导体芯片的芯片区域上， 在所述基板上形成模具层以包围所述第一和第二半导体芯片，在所述模具层中形成开口以露出所述下部传热图案的至少一部分，以在所述开口中形成热通路图案，并且形成 第二半导体芯片上的散热部件和要连接到热通路图案的模具层。

公开(公告)号：US20160372447A1

公开(公告)日：2016-12-22

申请号：US15250951

申请日：2016-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.

公开(公告)号：US20150155259A1

公开(公告)日：2015-06-04

申请号：US14619155

申请日：2015-02-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Gi-Jun PARK ,  Won-Keun KIM ,  Teak-Hoon LEE ,  Chang-Seong JEON ,  Young-Kun JEE

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.

Abstract translation: 半导体封装的基板包括具有第一表面和彼此面对的第二表面的第一布线基板，其上安装有半导体芯片的第一表面，第一支撑载体和将第二表面和第一支撑件连接的粘合膜 载体

公开(公告)号：US20140196280A1

公开(公告)日：2014-07-17

申请号：US14217744

申请日：2014-03-18

Applicant: Samsung Electronics Co., Ltd

Inventor： Chang-Seong JEON ,  Ho-Geon SONG ,  Mitsuo UMEMOTO ,  Sang-Sick PARK

IPC: H01L23/00 ,  H01L21/67

CPC classification number: H01L24/74 ,  H01L21/67 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32151 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7501 ,  H01L2224/7515 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/7598 ,  H01L2224/7901 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/53178 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.

Abstract translation: 制造倒装芯片封装的方法和装置包括将焊剂点到封装衬底的第一预备凸块上，通过焊剂将第一半导体芯片的初步凸点附着到封装衬底的第一初步凸块上，点焊焊剂 封装衬底的第二初步凸块，以及通过焊剂将第二半导体芯片的预备凸块附接到封装衬底的第二初级凸块。 因此，可以抑制在封装衬底的初步凸块上的焊剂的蒸发。

公开(公告)号：US20140008794A1

公开(公告)日：2014-01-09

申请号：US13900612

申请日：2013-05-23

Applicant: Samsung Electronics Co., Ltd

Inventor： Gi-Jun PARK ,  Won-Keun KIM ,  Teak-Hoon LEE ,  Chang-Seong JEON ,  Young-Kun JEE

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L21/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

Abstract: A substrate of a semiconductor package includes a first wiring substrate having a first surface and a second surface facing each other, the first surface having a semiconductor chip mounted thereon, a first support carrier, and an adhesive film connecting the second surface and the first support carrier.

Abstract translation: 半导体封装的基板包括具有第一表面和彼此面对的第二表面的第一布线基板，其上安装有半导体芯片的第一表面，第一支撑载体和将第二表面和第一支撑件连接的粘合膜 载体