公开(公告)号：US09478280B2

公开(公告)日：2016-10-25

申请号：US14742726

申请日：2015-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Duk Yu ,  Dong-Ku Kang ,  Dae-Yeal Lee

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C5/14

CPC classification number: G11C11/5628 ,  G11C5/143 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

Abstract: A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

Abstract translation: 半导体存储器件被配置为通过将验证电压的初始电压电平设置为第一电压电平并在第一时段期间提高验证电压来执行第一验证操作。 半导体存储器件包括存储程序数据的存储单元阵列，产生检测数据的传感器和比较程序数据和检测数据的条件确定单元。 控制逻辑单元包括验证操作控制器，被配置为基于程序数据和感测数据的比较结果选择性地执行用于通过将初始电压电平设置为第二电压来控制第二验证操作的第一验证控制操作 并且在第二时段期间增强验证电压，以及第二验证控制操作，用于通过将初始电压电平设置为第一电压电平来控制第二验证操作，并在第一时段期间升高验证电压。

公开(公告)号：US10133680B2

公开(公告)日：2018-11-20

申请号：US15183319

申请日：2016-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Ku Kang

IPC: G06F11/00 ,  G06F12/14 ,  G06F21/71 ,  G06F21/74

Abstract: In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

公开(公告)号：US09058890B2

公开(公告)日：2015-06-16

申请号：US13926297

申请日：2013-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Ku Kang

IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C11/5642

Abstract: A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.

Abstract translation: 提供闪存器件和读取方法，其中存储器单元被分成至少两组。 根据阈值电压分布选择存储单元。 根据第一读取操作，检测存储在所选择的存储器单元中的数据并且对应于至少两个组中的一个锁存数据。 第二读取操作检测并锁存与至少两个组中的另一组对应的存储单元的数据。 在第二次读取操作期间通过软判决算法处理数据。

公开(公告)号：US09858993B2

公开(公告)日：2018-01-02

申请号：US15601698

申请日：2017-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Ku Kang

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04 ,  G11C16/32

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n−1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state.

公开(公告)号：US09852795B2

公开(公告)日：2017-12-26

申请号：US15272776

申请日：2016-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Ku Kang ,  Sang-Yong Yoon ,  Joon-Suc Jang

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C29/00 ,  G11C7/10 ,  G11C29/44

CPC classification number: G11C16/0466 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/832 ,  G11C2029/4402 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of operating a nonvolatile memory device includes performing a first memory operation on a first memory block of a plurality of memory blocks and a curing operation on a portion of the first memory block when a status signal indicates a ready state of the nonvolatile memory device during an interval equal to or greater than a reference interval after the first memory operation is completed. The nonvolatile memory device includes the plurality of memory blocks, each memory block including a plurality of vertical strings extending in a vertical direction with respect to a substrate.

公开(公告)号：US09418747B2

公开(公告)日：2016-08-16

申请号：US14227314

申请日：2014-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Ku Kang ,  Seung-Bum Kim

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3459

Abstract: A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N−1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state.

Abstract translation: 非易失性存储器件包括存储单元阵列，该存储单元阵列包括设置在相应字线和位线的交点处的多个存储器单元，以及分别连接到位线的多页缓冲器，以及对在第一至第N编程中选定的存储器单元执行连续验证读操作， 逻辑状态（N> 2），其中，在连续验证读取操作中，通过在第一逻辑状态中编程的存储器单元的验证周期期间将位线预先充电到第一电平，将位线置于预充电状态 以第二到第（N-1）逻辑状态编程的存储器单元的验证期间的预充电状态，并且在以第N逻辑状态编程的存储单元的验证周期之后放电。

公开(公告)号：US09928006B2

公开(公告)日：2018-03-27

申请号：US15262478

申请日：2016-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Bum Kim ,  Dong-Ku Kang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.