公开(公告)号：US20180097006A1

公开(公告)日：2018-04-05

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L29/08 ,  H01L27/11582 ,  H01L29/10

CPC classification number: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US11430800B2

公开(公告)日：2022-08-30

申请号：US16839184

申请日：2020-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Seulye Kim ,  Dongkyum Kim ,  Sungjin Kim ,  Junghwan Kim ,  Chanhyoung Kim ,  Jihoon Choi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11558

Abstract: A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

公开(公告)号：US10453745B2

公开(公告)日：2019-10-22

申请号：US15160137

申请日：2016-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Jung Ho Kim ,  Dongkyum Kim ,  Seulye Kim ,  Jintae Noh ,  Hyun-Jin Shin ,  SeungHyun Lim

IPC: H01L23/522 ,  H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11424264B2

公开(公告)日：2022-08-23

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US10930739B2

公开(公告)日：2021-02-23

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dongkyum Kim ,  Sunggil Kim ,  Seulye Kim ,  Sangsoo Lee ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US20190206886A1

公开(公告)日：2019-07-04

申请号：US16298247

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L29/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/08

CPC classification number: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US20180261626A1

公开(公告)日：2018-09-13

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co. Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/24 ,  H01L27/11556 ,  H01L45/00

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US10658375B2

公开(公告)日：2020-05-19

申请号：US15975861

申请日：2018-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gukhyon Yon ,  Dongwoo Kim ,  Kihyun Hwang ,  Dongkyum Kim ,  Dongchul Yoo

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/24 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11575 ,  H01L45/00

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.

公开(公告)号：US10263006B2

公开(公告)日：2019-04-16

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.