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1.发明授权Image sensor including heterogeneous analog to digital convertor with different noise characteristics 有权图像传感器包括具有不同噪声特性的异构模数转换器公开(公告)号：US09537501B2
公开(公告)日：2017-01-03
申请号：US14546154
申请日：2014-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjong Lee , Byung-Jo Kim , Se-jun Kim
IPC: H01L27/146 , H03M1/12 , H03M1/56
CPC classification number: H03M1/1295 , H03M1/123 , H03M1/56
Abstract: An image sensor in accordance with exemplary embodiments of the inventive concept may include a pixel sensor array which includes an active pixel sensor and an optical black pixel sensor; a first analog to digital converter configured to convert a first sensing signal, which is provided from the active pixel sensor, to a first digital signal; a second analog to digital converter configured to convert a second sensing signal, which is provided from the optical black pixel sensor, to a second digital signal; and an output buffer configured to temporarily store and output the first digital signal and the second digital signal, wherein a plurality of noise characteristics of the second analog to digital converter is different from a plurality of noise characteristics of the first analog to digital converter.
Abstract translation: 根据本发明构思的示例性实施例的图像传感器可以包括像素传感器阵列，其包括有源像素传感器和光学黑色像素传感器; 第一模数转换器，被配置为将从有源像素传感器提供的第一感测信号转换为第一数字信号; 第二模数转换器，被配置为将从所述光学黑色像素传感器提供的第二感测信号转换为第二数字信号; 以及输出缓冲器，被配置为临时存储和输出第一数字信号和第二数字信号，其中第二模数转换器的多个噪声特性与第一模数转换器的多个噪声特性不同。
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公开(公告)号：US11825227B2
公开(公告)日：2023-11-21
申请号：US17941205
申请日：2022-09-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjong Lee , Yongsuk Choi
Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.
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公开(公告)号：US20220060647A1
公开(公告)日：2022-02-24
申请号：US17355443
申请日：2021-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeokjong Lee , Yongsuk Choi
Abstract: A correlated double sampling (CDS) circuit, an operating method thereof, and an image sensor including the CDS circuit are disclosed. The CDS circuit includes a first comparator configured to operate based on a first bias current, and compare, with a ramp signal, a pixel voltage that is output from a pixel, during a first period and a fourth period during which the pixel operates in a low conversion gain (LCG) mode, a second comparator configured to operate based on a second bias current, and compare, with the ramp signal, the pixel voltage output from the pixel, during a second period and a third period during which the pixel operates in a high conversion gain (HCG) mode, the second period being after the first period, the third period being after the second period, and the fourth period being after the third period.
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公开(公告)号：US12244954B2
公开(公告)日：2025-03-04
申请号：US18057252
申请日：2022-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeokjong Lee
IPC: H04N25/78 , H01L27/146 , H04N25/616 , H04N25/771
Abstract: Provided is a semiconductor device. The semiconductor device includes a first counter latch circuit configured to receive a count code and to latch the count code according to a comparison result signal; and a second counter latch circuit configured to receive the count code from the first counter latch circuit, and to latch the count code by using a plurality of first latches. The first latches are coupled in series to each other and are configured to operate to sequentially bypass values transmitted to the respective first latches.
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公开(公告)号：US20220078362A1
公开(公告)日：2022-03-10
申请号：US17459045
申请日：2021-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yunhwan Jung , Hyeokjong Lee , Sunyool Kang , Kyungmin Kim , Yunhong Kim , Ingyeong Shin
IPC: H04N5/355 , H04N5/378 , H04N5/3745
Abstract: An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230299111A1
公开(公告)日：2023-09-21
申请号：US18106143
申请日：2023-02-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyeokjong Lee , Minho Kwon , Kyongsoon Cho
IPC: H01L27/146 , H01L21/66 , H01L23/60 , H01L27/02 , H01L25/065
CPC classification number: H01L27/14636 , H01L22/14 , H01L23/60 , H01L27/02 , H01L25/0657
Abstract: A semiconductor device includes: a first semiconductor chip having an upper surface divided into a pixel array region and a connection region, wherein a plurality of pads are disposed in the connection region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the plurality of pads include: a first bonding pad for connection with an external circuit; and a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test, and wherein the second semiconductor chip includes: a first space overlapping the first bonding pad in a vertical direction and in which at least a portion of an electrostatic discharge protection circuit is formed.
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公开(公告)号：US11451731B2
公开(公告)日：2022-09-20
申请号：US16908980
申请日：2020-06-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jahyun Koo , Hyeokjong Lee
IPC: H04N5/3745 , H01L27/146 , H03M1/16 , H04N5/378 , H03M1/12 , H03M1/56 , H04N5/357 , H04N5/347 , H04N5/376 , H04N5/374
Abstract: An image sensor includes a pixel sensor outputting an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal that is time-axis length information; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.
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公开(公告)号：US09490833B2
公开(公告)日：2016-11-08
申请号：US14310065
申请日：2014-06-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeokjong Lee , Jinho Seo , Seogheon Ham
Abstract: Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal. The intensity of the ramp signal may increase or decrease in response to a ramp enable signal. The image sensor may include an analog-digital converter electrically connected to one of the columns of the pixels. The analog-digital converter may be configured to compare an output signal from the one of the columns of the pixels with the ramp signal, thereby generating time information. The analog-digital converter may be configured to convert the time information to digital information in response to a counter enable signal. An activation of the counter enable signal may be delayed by a predetermined time delay, compared with that of the ramp enable signal.
Abstract translation: 提供了一种图像传感器，其包括具有排列成行和列的多个像素的传感器阵列。 图像传感器可以包括可产生斜坡信号的斜坡信号发生器。 斜坡信号的强度可以响应于斜坡使能信号而增加或减小。 图像传感器可以包括电连接到像素的列之一的模拟数字转换器。 模拟数字转换器可以被配置为将来自像素的列之一的输出信号与斜坡信号进行比较，从而产生时间信息。 模拟数字转换器可以被配置为响应于计数器使能信号将时间信息转换成数字信息。 与斜坡使能信号相比，可以将计数器使能信号的激活延迟预定的时间延迟。
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9.发明申请SOLID STATE IMAGING DEVICES AND METHODS USING SINGLE SLOPE ADC WITH ADJUSTABLE SLOPE RAMP SIGNAL 审中-公开实体状态成像装置和使用单斜率ADC与可调斜率RAMP信号的方法公开(公告)号：US20140146210A1
公开(公告)日：2014-05-29
申请号：US14067293
申请日：2013-10-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeokjong Lee , Byung-Jo Kim , Jaejung Park , Yunjung Kim , Jinho Seo , Seung Hyun Lim , Seogheon Ham
IPC: H04N5/361
Abstract: A solid state imaging device includes a pixel array comprising a plurality of photoelectric conversion devices and an analog to digital conversion (ADC) circuit configured to convert an image signal received from the pixel array to a digital signal responsive to a ramp signal and a gain setting. The solid state imaging device further includes a ramp signal generator circuit configured to generate the ramp signal with a slope that varies responsive to a control signal and a dark level offset compensation circuit configured to generate the control signal responsive to the gain setting and a dark level measurement.
Abstract translation: 固态成像装置包括像素阵列，其包括多个光电转换装置和模数转换（ADC）电路，模拟数字转换（ADC）电路被配置为响应于斜坡信号和增益设置将从像素阵列接收的图像信号转换为数字信号 。 固态成像装置还包括斜坡信号发生器电路，该斜坡信号发生器电路被配置为产生具有响应于控制信号变化的斜率的斜坡信号和配置成响应于增益设置产生控制信号的暗电平偏移补偿电路和暗电平 测量。
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公开(公告)号：US12108173B2
公开(公告)日：2024-10-01
申请号：US18329169
申请日：2023-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yunhwan Jung , Hyeokjong Lee , Sunyool Kang , Kyungmin Kim , Yunhong Kim , Ingyeong Shin
IPC: H04N25/585 , H04N25/59 , H04N25/616 , H04N25/709 , H04N25/75 , H04N25/77 , H04N25/78
CPC classification number: H04N25/585 , H04N25/59 , H04N25/616 , H04N25/709 , H04N25/75 , H04N25/77 , H04N25/78
Abstract: An image sensor includes a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on an LCG reset signal or an LCG image signal being received as the pixel voltage, and receive the ramp signal through a third input node based on an HCG reset signal or an HCG image signal being received as the pixel voltage; and compare the ramp signal to the pixel voltage, and output the comparison signal corresponding to a comparison result.
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