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    Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device
    1.
    发明授权
    Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device 有权

    公开(公告)号：US11031071B2

    公开(公告)日：2021-06-08

    申请号：US16943473

    申请日：2020-07-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun Jun Yoon

    IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

    Abstract: A nonvolatile memory device includes a memory cell region including first metal pads and a memory cell array, and a peripheral circuit region including second metal pads, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted. The peripheral circuit region is vertically connected to the memory cell region by the metal pads directly.

    Nonvolatile memory devices, memory systems and related control methods
    2.
    发明授权
    Nonvolatile memory devices, memory systems and related control methods 有权
    非易失存储器件，存储器系统和相关控制方法

    公开(公告)号：US09520168B2

    公开(公告)日：2016-12-13

    申请号：US15151687

    申请日：2016-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghun Kwak ,  Hyun Jun Yoon ,  Dongkyo Shim

    IPC: G11C7/00 ,  G11C5/06 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/26

    Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.

    Abstract translation: 一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据， 发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部 设备。 非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态 完成。

    Method for operating non-volatile memory device and memory controller
    4.
    发明授权
    Method for operating non-volatile memory device and memory controller 有权
    操作非易失性存储器件和存储器控制器的方法

    公开(公告)号：US09117536B2

    公开(公告)日：2015-08-25

    申请号：US14088511

    申请日：2013-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Jun Yoon ,  Jaeyong Jeong ,  Myung-Hoon Choi ,  Kitae Park

    IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3422

    Abstract: An operating method for a non-volatile memory device includes applying first and second read voltages to a first word line to perform a read operation; counting first memory cells each having a threshold voltage belonging to a first voltage range between the first read voltage and the second read voltage; applying a third read voltage to the first word line sequentially after applying the second read voltage to count second memory cells each having a second threshold voltage belonging to a voltage range between the second read voltage and the third read voltage; comparing the number of first memory cells counted and the number of second memory cells counted; determining a fourth read voltage based on a result of the comparing; and applying the fourth read voltage to the first word line sequentially after applying the third read voltage.

    Abstract translation: 一种用于非易失性存储器件的操作方法包括：将第一和第二读取电压施加到第一字线以执行读取操作; 计数每个具有属于第一读取电压和第二读取电压之间的第一电压范围的阈值电压的第一存储器单元; 在施加第二读取电压以对具有属于第二读取电压和第三读取电压之间的电压范围的第二阈值电压的第二存储器单元计数时，顺序地向第一字线施加第三读取电压; 比较计数的第一存储器单元的数量和计数的第二存储单元的数量; 基于所述比较的结果确定第四读取电压; 以及在施加第三读取电压之后，将第四读取电压顺序地施加到第一字线。

    Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device
    5.
    发明授权
    Nonvolatile memory device, operating method of nonvolatile memory device, and storage device including nonvolatile memory device 有权

    公开(公告)号：US11017841B2

    公开(公告)日：2021-05-25

    申请号：US16677930

    申请日：2019-11-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun Jun Yoon

    IPC: G11C7/10 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/06 ,  G11C11/56 ,  G11C11/4074

    Abstract: A nonvolatile memory device includes a memory cell array that includes memory cells arranged in rows and columns, row decoder circuitry that is connected to the rows of the memory cells through word lines and controls voltages of the word lines, and page buffer circuitry that is connected to the columns of the memory cells through bit lines and includes first transistors configured to sense voltages of the bit lines and second transistors configured to invert and sense the voltages of the bit lines. The page buffer circuitry is configured to obtain first values by performing a first sensing operation on first bit lines of the bit lines through the first transistors and obtain second values by performing a second sensing operation on the second bit lines of the bit lines through the second transistors, wherein the first values or the second values are inverted.

    Nonvolatile memory device and a method of reading the same
    8.
    发明授权
    Nonvolatile memory device and a method of reading the same 有权

    公开(公告)号：US10210936B2

    公开(公告)日：2019-02-19

    申请号：US15398014

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun Jun Yoon ,  Ji-Sang Lee

    IPC: G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/20

    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, an address decoder configured to be connected to the memory cells through a plurality of word lines and to provide select or unselect read voltages to the word lines, and a control logic configured to control the address decoder to perform a plurality of read sequences in a continuous read mode and to adjust a word line setup start point in at least one of the read sequences to be different than a word line setup start point in at least one of the other read sequences, wherein the word line setup start point is a time at which the select or unselect read voltages begin to be provided to the word lines.

    Nonvolatile memory device and memory system including the same
    9.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US09251904B2

    公开(公告)日：2016-02-02

    申请号：US14458567

    申请日：2014-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doohyun Kim ,  Hyun Jun Yoon ,  Donghun Kwak ,  Kitae Park ,  Changyeon Yu

    IPC: G11C29/56 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/56

    Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

    Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器，向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑，使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。

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