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    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND SELECT DEVICES AND METHODS THEREOF
    4.
    发明申请
    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND SELECT DEVICES AND METHODS THEREOF 有权
    具有垂直位线和选择器件的读/写元件的三维阵列的非易失性存储器及其方法

    公开(公告)号：US20140335671A1

    公开(公告)日：2014-11-13

    申请号：US14339895

    申请日：2014-07-24

    Applicant: SANDISK 3D LLC

    Inventor： George Samachisa ,  Johann Alsmeier

    IPC: H01L27/115

    CPC classification number: H01L27/11551 ,  G11C5/025 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  H01L21/306 ,  H01L21/76224 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

    Abstract: A three-dimensional memory is formed as an array of memory elements that are formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines acting as local vertical bit lines through the multiple layers of planes which together with arrays of word lines on each plane are used to access the memory elements. The three-dimensional memory is formed over a CMOS substrate with an intermediate pillar select layer. The pillar select layer is formed with a plurality of pillar select devices which are switching transistors formed outside the CMOS and serve to switch selected rows of pillar lines to corresponding metal lines on the substrate.

    Abstract translation: 形成三维存储器作为形成在位于半导体衬底上方不同距离的多层平面上的存储元件的阵列。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括通过多层平面的作为局部垂直位线的柱线的二维阵列，每个平面上的字线阵列被用于访问存储器元件。 在具有中间柱选择层的CMOS衬底上形成三维存储器。 柱选择层形成有多个柱选择器件，其是形成在CMOS外部的开关晶体管，用于将所选择的行列切换到衬底上相应的金属线。

    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF
    6.
    发明申请
    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF 有权
    具有读取/写入元件的3D阵列的非易失性存储器及其读取/写入电路及其方法

    公开(公告)号：US20140022848A1

    公开(公告)日：2014-01-23

    申请号：US13973218

    申请日：2013-08-22

    Applicant: SANDISK 3D LLC

    Inventor： George Samachisa ,  Luca Fasoli ,  Yan Li ,  Tianhong Yan

    IPC: G11C16/06

    CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0097 ,  G11C16/06 ,  G11C2013/0054 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1675

    Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

    Abstract translation: 三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。 在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。 提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。 当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

    Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof
    8.
    发明授权
    Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof 有权
    具有具有阶梯字线和垂直位线的3D阵列架构的非易失性存储器及其方法

    公开(公告)号：US09147439B2

    公开(公告)日：2015-09-29

    申请号：US13840759

    申请日：2013-03-15

    Applicant: SanDisk 3D LLC

    Inventor： Raul Adrian Cernea ,  George Samachisa

    IPC: G11C5/02 ,  G11C5/06 ,  H01L27/105 ,  H01L21/768 ,  G06F12/02 ,  G11C7/18 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  G06F12/0238 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L21/76877 ,  H01L27/1052 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

    Abstract: In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.

    Abstract translation: 在具有以由具有x，y和z方向的直角坐标定义的三维图案中布置的存储元件的3D非易失性存储器中，并且具有多个平行平面，从底平面到在z方向上堆叠的顶平面 半导体衬底; 多个局部位线沿Z方向延伸穿过多个层并且布置在具有沿x方向和y方向的行的位线柱的二维矩形阵列中; 所述3D非易失性存储器还具有沿着y方向间隔开并且在多个位置处与所述多个位线柱之间和分离的多个阶梯字线，各个阶梯字线各自具有一系列交替的台阶和提升板 分别在x方向和z方向上在z方向上跨越多个平面横跨每个平面中的段。

    3D non-volatile memory having low-current cells and methods
    9.
    发明授权
    3D non-volatile memory having low-current cells and methods 有权
    具有低电流单元和方法的3D非易失性存储器

    公开(公告)号：US09064547B2

    公开(公告)日：2015-06-23

    申请号：US14196956

    申请日：2014-03-04

    Applicant: SanDisk 3D LLC

    Inventor： Raul Adrian Cernea ,  Yung-Tin Chen ,  George Samachisa

    IPC: G11C5/02 ,  G11C5/06 ,  G11C13/00 ,  H01L27/24 ,  G11C5/04 ,  H01L45/00

    CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C5/04 ,  G11C13/0002 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/149

    Abstract: A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.

    Abstract translation: 非易失性存储器的3D阵列具有在字线和位线之间的交叉处访问的每个读/写元件。 读/写元件形成具有包围氧化物核心的R / W材料的外壳的管状电极。 在矩形形式中，电极的一侧接触字线，另一侧接触位线。 壳体的厚度而不是与字线和位线接触的表面积决定了传导截面，因此决定了电阻。 通过调整外壳的厚度，独立于与字线或位线的接触面积，每个读/写元件可以以大大增加的电阻工作，因此电流大大降低。 还描述了使用这种管状R / W元件3D阵列来制造3D阵列的过程。

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