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公开(公告)号：US10128261B2
公开(公告)日：2018-11-13
申请号：US14613956
申请日：2015-02-04
发明人： Raghuveer S. Makala , Rahul Sharangpani , Sateesh Koka , Genta Mizuno , Naoki Takeguchi , Senaka Krishna Kanakamedala , George Matamis , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11556 , H01L29/49 , H01L21/28 , H01L27/11563 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L21/3213 , H01L21/768 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11568
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
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2.发明授权公开(公告)号：US09842907B2
公开(公告)日：2017-12-12
申请号：US14869406
申请日：2015-09-29
发明人： Raghuveer S. Makala , Sateesh Koka , Zhenyu Lu , Somesh Peri , Rahul Sharangpani
IPC分类号： H01L21/8239 , H01L29/49 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/788 , H01L21/28 , H01L21/285 , H01L27/11568
CPC分类号： H01L29/4975 , H01L21/28273 , H01L21/28282 , H01L21/28518 , H01L27/11524 , H01L27/11556 , H01L27/11568 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-semiconductor alloy portion is formed in each backside recess by reacting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by an etch to electrically isolate cobalt-containing alloy portions located in different backside recesses. Electrically conductive layers including a respective cobalt-semiconductor alloy portion can be employed as word lines of a three-dimensional memory device.
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3.发明申请公开(公告)号：US20170278571A1
公开(公告)日：2017-09-28
申请号：US15078555
申请日：2016-03-23
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
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公开(公告)号：US09754958B2
公开(公告)日：2017-09-05
申请号：US14927708
申请日：2015-10-30
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/3065 , H01L29/788 , H01L21/306
CPC分类号： H01L27/11582 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
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公开(公告)号：US09679906B2
公开(公告)日：2017-06-13
申请号：US14823274
申请日：2015-08-11
发明人： Zhenyu Lu , Johann Alsmeier , Daxin Mao , Wenguang Shi , Sateesh Koka , Raghuveer S. Makala , George Matamis , Yao-Sheng Lee , Chun Ge
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L27/11524 , H01L27/11556
CPC分类号： H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582
摘要： A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.
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公开(公告)号：US09627399B2
公开(公告)日：2017-04-18
申请号：US14808229
申请日：2015-07-24
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/1157 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/02
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.
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7.发明授权公开(公告)号：US09627395B2
公开(公告)日：2017-04-18
申请号：US14619691
申请日：2015-02-11
IPC分类号： H01L27/115 , H01L21/324 , H01L21/768 , H01L21/28 , H01L23/522 , H01L29/788 , H01L27/11556
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/76802 , H01L21/76877 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/7883
摘要： A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.
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8.发明授权公开(公告)号：US09570460B2
公开(公告)日：2017-02-14
申请号：US14620674
申请日：2015-02-12
IPC分类号： H01L21/336 , H01L27/115 , H01L21/311 , H01L21/28 , H01L21/02
CPC分类号： H01L27/11582 , H01L21/02063 , H01L21/28273 , H01L21/28282 , H01L21/31116 , H01L21/31144 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.
摘要翻译： 制造半导体器件的方法包括在衬底上形成第一材料和第二材料的交替层的堆叠，蚀刻堆叠以在堆叠中形成至少一个开口，使得受损区域位于 所述至少一个开口在所述至少一个开口的侧壁上形成掩蔽层，同时所述至少一个开口的底表面未被掩蔽层覆盖，并且进一步蚀刻所述至少一个开口的底表面去除 受损区域。
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公开(公告)号：US09530791B1
公开(公告)日：2016-12-27
申请号：US14883966
申请日：2015-10-15
发明人： Yanli Zhang , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115
摘要： A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.
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10.发明授权Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack 有权具有阻塞电介质的三维存储器件具有增强的防止氟侵蚀的保护公开(公告)号：US09515079B2
公开(公告)日：2016-12-06
申请号：US14751922
申请日：2015-06-26
发明人： Sateesh Koka , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , Yao-Sheng Lee , George Matamis , Wei Zhao
IPC分类号： H01L27/115 , H01L21/223 , H01L21/02 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/02164 , H01L21/02178 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/02356 , H01L21/2236 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7883 , H01L29/792
摘要： Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.
摘要翻译： 提供了用于阻止或减少氟扩散的阻挡电介质结构和/或较厚的阻挡金属膜。 可以在延伸穿过电绝缘层和牺牲材料层的存储器堆叠结构中形成隔离电介质层作为存储膜的外层。 在通过去除牺牲材料层形成背面凹槽之后，可以例如通过等离子体处理或热处理将掺杂剂引入到阻挡介电层的物理暴露部分中，以形成可以减少或防止氟扩散的氮氧化硅区域。 或者或另外，可以在背面凹部中形成一组金属氧化物阻挡介电材料部分，以延迟或防止氟扩散。 为了最小化对形成在背面凹槽中的导电层的不利影响，阻挡电介质材料部分可以从用于形成背面凹槽的沟槽侧向凹入。
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