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    Metal word lines for three dimensional memory devices
    4.
    发明授权
    Metal word lines for three dimensional memory devices 有权
    用于三维存储器件的金属字线

    公开(公告)号：US09570455B2

    公开(公告)日：2017-02-14

    申请号：US14553207

    申请日：2014-11-25

    申请人： SanDisk Technologies, Inc.

    发明人： Rahul Sharangpani ,  Raghuveer S. Makala ,  Senaka Krishna Kanakamedala ,  Sateesh Koka ,  Yao-Sheng Lee ,  George Matamis

    IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L29/49 ,  H01L21/285 ,  H01L21/02

    CPC分类号： H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28556 ,  H01L21/28568 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/7883

    摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.

    摘要翻译： 一种制造单片三维NAND串的方法，包括在所述衬底的主表面上形成绝缘的第一材料和不同于所述第一材料的牺牲第二材料的交替层的堆叠，在所述堆叠中形成前侧开口，至少形成 在前侧开口中的一个电荷存储区域，并且在前侧开口中的至少一个电荷存储区域上形成隧道电介质层。 该方法还包括在前侧开口的隧道电介质层的上方形成半导体通道，在堆叠中形成背面开口，并选择性地移除第二材料层的至少一部分，以在相邻的第一材料层之间形成背面凹槽。 该方法还包括在后侧凹槽中形成导电蛤形成核衬砌区域，并通过相应的导电蛤形成核区域中的背侧开口选择性地形成钌控制栅电极。

    Three-dimensional memory devices having a single layer channel and methods of making thereof
    5.
    发明授权
    Three-dimensional memory devices having a single layer channel and methods of making thereof 有权
    具有单层通道的三维存储器件及其制造方法

    公开(公告)号：US09530785B1

    公开(公告)日：2016-12-27

    申请号：US14804564

    申请日：2015-07-21

    申请人： SanDisk Technologies, Inc.

    发明人： Sateesh Koka ,  Zhenyu Lu ,  Wei Zhao ,  Ching-Huang Lu ,  Henry Chien ,  Yingda Dong ,  Raghuveer S. Makala ,  Somesh Peri ,  Rahul Sharangpani ,  George Matamis ,  Yuichi Ikezono ,  Hiroyuki Ogawa

    IPC分类号： H01L29/76 ,  H01L27/115

    CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

    摘要： A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

    摘要翻译： 用于三维器件的存储器堆叠结构包括交替堆叠的绝缘体层和间隔物材料层。 通过交替堆叠形成存储器开口。 在存储器开口中形成记忆材料层，隧道介电层和氧化硅衬垫。 随后在隧道电介质层上形成牺牲衬垫。 层叠堆叠被各向异性蚀刻以物理地暴露存储器开口下方的衬底的半导体表面。 可以在各向异性蚀刻之前或之后去除牺牲衬垫。 在各向异性蚀刻之后去除氧化硅衬垫。 可以将半导体沟道层直接沉积在隧道电介质层上作为单个材料层而没有任何界面。

    Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure
    6.
    发明授权
    Metal-semiconductor alloy region for enhancing on current in a three-dimensional memory structure 有权
    用于增强三维记忆结构中的电流的金属 - 半导体合金区域

    公开(公告)号：US09524977B2

    公开(公告)日：2016-12-20

    申请号：US14687403

    申请日：2015-04-15

    申请人： SanDisk Technologies, Inc.

    发明人： Rahul Sharangpani ,  Raghuveer S. Makala ,  Sateesh Koka ,  Tomohiro Kubo ,  Junichi Ariyoshi ,  George Matamis

    IPC分类号： H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel.

    摘要翻译： 通过在位于衬底内的垂直半导体沟道和水平半导体沟道之间形成金属 - 半导体合金区域，可以减小三维存储堆栈结构中的半导体沟道的电阻。 金属 - 半导体合金区域可以通过在形成记忆膜之后在存储器开口下面的半导体衬底中的一部分半导体材料层凹陷来形成，在凹陷区域中选择性地沉积金属材料，沉积垂直半导体沟道，以及 使沉积的金属材料与半导体材料层和垂直半导体沟道的相邻部分反应。 在金属材料的选择性沉积之前，可以在记忆膜上形成牺牲介电材料层。 可以在单个沉积工艺中形成垂直半导体沟道，从而消除其中的任何界面并使垂直半导体沟道的电阻最小化。

    Method of making a three dimensional NAND device
    7.
    发明授权
    Method of making a three dimensional NAND device 有权
    制造三维NAND器件的方法

    公开(公告)号：US09305849B1

    公开(公告)日：2016-04-05

    申请号：US14539372

    申请日：2014-11-12

    申请人： SanDisk Technologies, Inc.

    发明人： Masanori Tsutsumi ,  Shigehiro Fujino ,  Sateesh Koka ,  Senaka Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  George Matamis ,  Wei Zhao

    IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/8239 ,  H01L21/283 ,  H01L27/115 ,  H01L21/822

    CPC分类号： H01L21/8239 ,  H01L21/28282 ,  H01L21/8221 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    摘要： A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

    摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的基本垂直于基板的主表面延伸的端部，基本上平行于基板的主表面延伸的多个控制栅电极，电荷存储材料 位于多个控制栅电极和半导体沟道之间的层，位于电荷存储材料层和半导体沟道之间的隧道电介质，以及包含多个蛤状部分的阻挡电介质，每个具有两个水平部分的垂直部分 一部分。 多个控制栅电极中的每一个至少部分地位于蛤状阻挡电介质中的开口中，以及多个分立的覆盖氧化物段，其嵌入部分电荷存储材料层的厚度并位于阻挡电介质 和电荷存储材料层。

    THREE-DIMENSIONAL MEMORY DEVICES CONTAINING MEMORY BLOCK BRIDGES
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICES CONTAINING MEMORY BLOCK BRIDGES 有权
    包含记忆块桥的三维存储器件

    公开(公告)号：US20170047334A1

    公开(公告)日：2017-02-16

    申请号：US14823274

    申请日：2015-08-11

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Zhenyu Lu ,  Johann Alsmeier ,  Daxin Mao ,  Stephen Shi ,  Sateesh Koka ,  Raghuveer S. Makala ,  George Matamis ,  Yao-Sheng Lee ,  Chun Ge

    IPC分类号： H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

    摘要： A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

    摘要翻译： 单片三维存储器件包括包含位于衬底上的多个存储子块的第一存储块。 每个存储器子块包括一组存储器堆叠结构和交替层的一部分横向围绕该组存储器堆叠结构。 交替层包括绝缘层和导电层。 相邻的一对存储器子块的第一部分通过背面接触通孔结构沿着第一水平方向彼此横向间隔开。 交替层的子集在相邻的一对存储子块的第二部分之间通过沿着第二水平方向横向间隔开的背侧接触通孔结构的两个部分之间的桥接区域中的间隙连续地延伸，以提供 在相邻的一对存储器子块之间的连接部分。