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    WAFER LEVEL MICROELECTRONIC PACKAGING WITH DOUBLE ISOLATION
    2.
    发明申请
    WAFER LEVEL MICROELECTRONIC PACKAGING WITH DOUBLE ISOLATION 审中-公开
    具有双重隔离的水平微电子封装

    公开(公告)号：US20060081983A1

    公开(公告)日：2006-04-20

    申请号：US10711945

    申请日：2004-10-14

    Applicant: Giles Humpston ,  Bruce McWilliams

    Inventor： Giles Humpston ,  Bruce McWilliams

    IPC: H01L23/52

    CPC classification number: B81B7/0077 ,  G01N21/3504 ,  H01L21/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: A microelectronic package may include front and rear covers overlying the front and rear surfaces of a microelectronic element such as an infrared sensor and spaces between the microelectronic element and the covers to provide thermal isolation. A sensing unit including a microelectronic package may include a reflector spaced from the front cover to provide an analyte space, and the microelectronic element may include an emitter and a detector so that radiation directed from the emitter will be reflected by the sensor to the detector, and such radiation will be affected by the properties of the analyte in the analyte space. Such a unit provides a compact, economical chemical sensor. Other packages include elements such as valves for passing fluids into and out of the spaces within the package itself.

    Abstract translation: 微电子封装可以包括覆盖微电子元件的前表面和后表面的前盖和后盖，例如红外传感器和微电子元件和盖之间的空间，以提供热隔离。 包括微电子封装的感测单元可以包括与前盖隔开以提供分析物空间的反射器，并且微电子元件可以包括发射器和检测器，使得从发射器引导的辐射将被传感器反射到检测器， 并且这种辐射将受分析物空间中分析物的性质的影响。 这种单元提供了紧凑，经济的化学传感器。 其他包装包括诸如用于使流体进入和流出包装内的空间的阀门的元件。

    CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS
    5.
    发明申请
    CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS 有权
    具有可调节晶体管体偏置的电路装置和方法

    公开(公告)号：US20120327725A1

    公开(公告)日：2012-12-27

    申请号：US13167625

    申请日：2011-06-23

    Applicant: Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    Inventor： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    IPC: G11C7/00 ,  G05F1/10

    CPC classification number: G11C11/412

    Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

    Abstract translation: 公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。 偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。 特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。 一个或多个发电电路可以产生多个偏置电压。 偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

    Circuit devices and methods having adjustable transistor body bias
    8.
    发明授权
    Circuit devices and methods having adjustable transistor body bias 有权
    具有可调节晶体管体偏置的电路器件和方法

    公开(公告)号：US08995204B2

    公开(公告)日：2015-03-31

    申请号：US13167625

    申请日：2011-06-23

    Applicant: Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    Inventor： Lawrence T. Clark ,  Bruce McWilliams ,  Robert Rogenmoser

    IPC: G11C7/00 ,  G11C11/412

    CPC classification number: G11C11/412

    Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

    Abstract translation: 公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。 偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。 特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。 一个或多个发电电路可以产生多个偏置电压。 偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

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