公开(公告)号：US20100208443A1

公开(公告)日：2010-08-19

申请号：US12707996

申请日：2010-02-18

申请人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

发明人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

IPC分类号： H05K7/00

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US20130114223A1

公开(公告)日：2013-05-09

申请号：US13463317

申请日：2012-05-03

申请人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

发明人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

IPC分类号： H05K1/18

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US20100084773A1

公开(公告)日：2010-04-08

申请号：US12572326

申请日：2009-10-02

申请人： Satoshi ITAYA ,  Dai SASAKI ,  Mitsuaki KATAGIRL

发明人： Satoshi ITAYA ,  Dai SASAKI ,  Mitsuaki KATAGIRL

IPC分类号： H01L23/49 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85148 ,  H01L2224/8518 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.

摘要翻译： 布线基板和安装在布线基板上的半导体芯片通过接合线连接在一起。 从半导体芯片的每一端到设置在布线基板上的引线接合焊盘的距离小于半导体芯片的高度。

公开(公告)号：US20120263487A1

公开(公告)日：2012-10-18

申请号：US13446136

申请日：2012-04-13

申请人： Satoshi ITAYA

发明人： Satoshi ITAYA

IPC分类号： G03G15/20

CPC分类号： G03G15/2053 ,  G03G15/2032 ,  G03G2215/0132

摘要： The fixing device according to the embodiment includes a fixing member which is heated at predetermined temperature for a fixing, a press member which is configured to move relative to the fixing member and to contact with the fixing member so as to transport an image bearing medium by cooperating with the fixing member during a fixing, driving member which moves the fixing member and press member in a plurality of speeds including predetermined speed for during the fixing, pressure change member which is configured to change a pressure between the fixing member and the press member, and control member which controls the driving member and the pressure change member, when the fixing member and the press member are idle for fixing, to reduce the pressure and the speed of the fixing member and the press member compared with during the fixing.

摘要翻译： 根据实施例的定影装置包括在预定温度下被加热以进行固定的固定构件，被构造成相对于固定构件移动并与固定构件接触的按压构件，以便通过 在固定期间与固定构件配合的驱动构件，其在固定期间以包括预定速度的多个速度移动固定构件和按压构件;驱动构件，其构造成改变固定构件和压力构件之间的压力 以及控制构件，其在固定构件和压力构件怠速固定时控制驱动构件和压力变化构件，以减小固定构件和压力构件的压力和速度。