公开(公告)号：US20130114223A1

公开(公告)日：2013-05-09

申请号：US13463317

申请日：2012-05-03

申请人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

发明人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

IPC分类号： H05K1/18

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US20100208443A1

公开(公告)日：2010-08-19

申请号：US12707996

申请日：2010-02-18

申请人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

发明人： Satoshi ITAYA ,  Satoshi ISA ,  Mitsuaki KATAGIRI ,  Dai SASAKI

IPC分类号： H05K7/00

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US20100193933A1

公开(公告)日：2010-08-05

申请号：US12687311

申请日：2010-01-14

申请人： Yu HASEGAWA ,  Mitsuaki KATAGIRI ,  Satoshi ISA ,  Ken IWAKURA ,  Dai SASAKI

发明人： Yu HASEGAWA ,  Mitsuaki KATAGIRI ,  Satoshi ISA ,  Ken IWAKURA ,  Dai SASAKI

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85007 ,  H01L2224/85051 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48132 ,  H01L2924/00012 ,  H01L2924/20757 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

摘要翻译： 在本发明的半导体器件中，第二半导体芯片堆叠在其中心区域具有多个接合焊盘的第一半导体芯片上，其间插入有接合层。 通过穿过第一和第二半导体芯片之间的空间，分别连接到第一半导体芯片的多个接合焊盘的多条引线在第一半导体芯片的外围边缘被引出到外部。 在第一半导体芯片上的区域中设置用于保持多条电线的至少一个子集的保持构件，该区域包括通过使用不同于接合层的材料，在接合焊盘与第一半导体芯片的周边边缘之间的中间点 使得电线的子集通常位于第一半导体芯片和第二半导体芯片之间的间隔的中心。

公开(公告)号：US20110180934A1

公开(公告)日：2011-07-28

申请号：US13014235

申请日：2011-01-26

申请人： Hiromasa TAKEDA ,  Satoshi ISA ,  Mitsuaki KATAGIRI

发明人： Hiromasa TAKEDA ,  Satoshi ISA ,  Mitsuaki KATAGIRI

IPC分类号： H01L23/48

CPC分类号： H01L24/49 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68331 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively.

摘要翻译： 半导体器件可以包括：经由间隙彼此分离的第一和第二布线板; 半导体芯片; 第一组和第二组电极垫; 以及第一组和第二组连接垫。 半导体芯片固定在第一和第二布线板的上表面上，并且具有与间隙相邻的第一部分。 第一和第二组电极焊盘设置在第一部分上。 第一和第二组电极焊盘分别与第一和第二布线板的侧表面相对准。 第一和第二布线板的侧表面彼此面对。 第一和第二组连接焊盘分别设置在第一和第二布线板的下表面上。 第一和第二组连接焊盘分别与第一和第二布线板的侧表面相对准。

公开(公告)号：US20080224311A1

公开(公告)日：2008-09-18

申请号：US12126681

申请日：2008-05-23

申请人： Satoshi ISA ,  Mitsuaki KATAGIRI ,  Fumiyuki OSANAI

发明人： Satoshi ISA ,  Mitsuaki KATAGIRI ,  Fumiyuki OSANAI

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

公开(公告)号：US20100188878A1

公开(公告)日：2010-07-29

申请号：US12693246

申请日：2010-01-25

申请人： Hiromasa TAKEDA ,  Kyoichi NAGATA ,  Satoshi ISA ,  Mitsuaki KATAGIRI

发明人： Hiromasa TAKEDA ,  Kyoichi NAGATA ,  Satoshi ISA ,  Mitsuaki KATAGIRI

IPC分类号： G11C5/06 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/105

摘要： A semiconductor device includes a first pad that supplies power to sense amplifiers, a second pad that supplies power to a first circuit connected to the sense amplifiers, a third pad that receives a signal input or outputs a signal at a frequency equal to or higher than a first frequency, and a fourth pad that receives a signal input or outputs a signal at a second frequency lower than the first frequency. The first pad is arranged between and adjacent to the second pads respectively, or arranged between and adjacent to the second and fourth pads respectively. Additionally, the first pad is arranged between the third pads, which are respectively arranged on both sides of the first pad, to be adjacent to the second pad so as to hold the second pad or to be adjacent to the fourth pad so as to hold the fourth pad.

摘要翻译： 半导体器件包括向读出放大器供电的第一焊盘，向连接到读出放大器的第一电路供电的第二焊盘;接收信号输入或输出等于或高于 第一频率和第四垫，其接收输入或输出低于第一频率的第二频率的信号的信号。 第一焊盘分别布置在第二焊盘之间并与之相邻，或者分别布置在第二焊盘之间并且与第二焊盘相邻。 此外，第一焊盘被布置在第三焊盘之间，第三焊盘分别布置在第一焊盘的两侧，以与第二焊盘相邻，以便保持第二焊盘或与第四焊盘相邻以便保持 第四垫。

公开(公告)号：US20070001299A1

公开(公告)日：2007-01-04

申请号：US11531167

申请日：2006-09-12

申请人： Wataru KIKUCHI ,  Toshio SUGANO ,  Satoshi ISA

发明人： Wataru KIKUCHI ,  Toshio SUGANO ,  Satoshi ISA

IPC分类号： H01L23/34

CPC分类号： H01L23/5386 ,  H01L23/5383 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01055 ,  H01L2924/01068 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.

摘要翻译： 堆叠的半导体封装包括两个半导体芯片（11,12），每个半导体芯片具有设置有以预定图案布置的多个芯片引脚的安装表面。 半导体芯片安装在基板（13）的相对表面上，使得安装表面通过基板相互面对。 基板设置有形成在除了芯片安装区域之外的区域中并且以与预定图案相同的图案布置的多个封装销。 半导体芯片的一对相应的芯片引脚通过使用长度相等的分支线连接到在其间的中间位置处形成的通孔。 通孔通过公共导线连接到与连接到通孔的芯片引脚对应的封装引脚。

公开(公告)号：US20110291295A1

公开(公告)日：2011-12-01

申请号：US13113560

申请日：2011-05-23

申请人： Satoshi ISA ,  Hiromasa Takeda ,  Kouji Sato

发明人： Satoshi ISA ,  Hiromasa Takeda ,  Kouji Sato

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012

摘要： A semiconductor device comprises a substrate, pluralities of first and second external electrodes formed in two end portions of one surface of the substrate, a first semiconductor chip mounted on the other surface of the substrate, the first semiconductor chip having an electrode pad row formed in one end portion of one surface of the first semiconductor chip and electrically connected to the first external electrodes, the first semiconductor chip being disposed so that the one end portion of the first semiconductor chip is positioned on an end portion on which the first external electrodes of the substrate are formed, and a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having an electrode pad row formed in one end portion of one surface of the second semiconductor chip and electrically connected to the second external electrode, the second semiconductor chip being disposed so that the one end portion of the second semiconductor chip is positioned on an end portion on which the second external electrodes of the substrate are formed.

摘要翻译： 半导体器件包括：衬底，形成在衬底的一个表面的两个端部中的多个第一和第二外部电极，安装在衬底的另一个表面上的第一半导体芯片，第一半导体芯片，其形成有电极焊盘排 第一半导体芯片的一个表面的一个端部电连接到第一外部电极，第一半导体芯片被布置成使得第一半导体芯片的一个端部位于第一半导体芯片的第一外部电极 形成基板，并且安装在第一半导体芯片上的第二半导体芯片，第二半导体芯片具有形成在第二半导体芯片的一个表面的一个端部中并电连接到第二外部电极的电极焊盘列，第二半导体芯片 半导体芯片被布置成使得第二半导体芯片i的一个端部 s位于其上形成有基板的第二外部电极的端部。