公开(公告)号：US07276435B1

公开(公告)日：2007-10-02

申请号：US11445657

申请日：2006-06-02

申请人： Scott K. Pozder ,  Kevin J. Hess ,  Ruiqi Tian ,  Edward O. Travis ,  Trent S. Uehling ,  Brett P. Wilkerson ,  Katie C. Yu

发明人： Scott K. Pozder ,  Kevin J. Hess ,  Ruiqi Tian ,  Edward O. Travis ,  Trent S. Uehling ,  Brett P. Wilkerson ,  Katie C. Yu

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014

摘要： An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

摘要翻译： 集成电路在顶表面上具有金属凸块，当形成金属凸块时，在底层上产生潜在的破坏性应力。 确保底层金属互连层中的最小金属浓度得以实现，以减少破坏作用。 最低金属浓度在角落最高，接下来沿着边界不在拐角处，接下来是内部。 通常在金属凸块下方的互连层中的区域需要比不在凸块下方的相邻区域更多的浓度。 对于远离集成电路表面的金属互连层，需要较小的浓度。 所需的金属浓度通过首先尝试相对简单的解决方案实现。 如果没有效果，则尝试不同的方法，直到达到最小浓度，或直到最后一次尝试。

公开(公告)号：US20110269300A1

公开(公告)日：2011-11-03

申请号：US13182568

申请日：2011-07-14

申请人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： H01L21/20 ,  G06F17/50

CPC分类号： H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

公开(公告)号：US08003539B2

公开(公告)日：2011-08-23

申请号：US11650253

申请日：2007-01-04

申请人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： H01L21/311

CPC分类号： H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

公开(公告)号：US07470624B2

公开(公告)日：2008-12-30

申请号：US11651253

申请日：2007-01-08

申请人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： H01L21/302

CPC分类号： H01L21/84 ,  G06F2217/12 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66651 ,  Y02P90/265

摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

摘要翻译： 提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301） （b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307） 在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

公开(公告)号：US20080168417A1

公开(公告)日：2008-07-10

申请号：US11650254

申请日：2007-01-04

申请人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： G06F17/50

CPC分类号： H01L29/045 ,  G06F2217/12 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/31053 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66651 ,  Y02P90/265

摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).

摘要翻译： 提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301） （b）从第一数据组导出第一沟槽CMP掩模集（307）和第一外延生长掩模组（309），其中通过去除子集（305）从第一数据集导出第一外延生长掩模集合， 由所述第一数据集定义并且将所述瓦片的子集合合到所述第一外延生长掩模集合中的所述瓦片; 以及（c）重新配置第一沟槽CMP掩模集合以考虑第一外延生长掩模集合，从而限定第二沟槽CMP掩模集合（308）。

公开(公告)号：US06593226B2

公开(公告)日：2003-07-15

申请号：US09906874

申请日：2001-07-17

申请人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian ,  Robert E. Boone ,  Alfred J. Reich

发明人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian ,  Robert E. Boone ,  Alfred J. Reich

IPC分类号： H01L214763

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  Y10S438/926

摘要： Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

公开(公告)号：US08722519B2

公开(公告)日：2014-05-13

申请号：US13182568

申请日：2011-07-14

申请人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： H01L27/07

CPC分类号： H01L21/02595 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）创建限定多晶硅沉积工艺的一组瓦片的数据集（301）; （b）从所述数据集中导出多晶硅沉积掩模组（311），其中所述多晶硅沉积掩模组包括多个多晶硅瓦（303）; （c）从所述数据集中导出外延生长掩模组（321），其中所述外延生长掩模组包括多个外延片（305）; 和（d）使用所述多晶硅沉积掩模组和所述外延生长掩模组来制造半导体器件（331）; 其中通过使用在外延沉积掩模组中限定的瓦片图案的至少一部分的数据集中定义的瓦片图案的至少一部分，从所述数据集中导出所述外延生长掩模组。

公开(公告)号：US06611045B2

公开(公告)日：2003-08-26

申请号：US09873810

申请日：2001-06-04

申请人： Edward O. Travis ,  Sejal N. Chheda ,  Ruiqi Tian

发明人： Edward O. Travis ,  Sejal N. Chheda ,  Ruiqi Tian

IPC分类号： H01L23544

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

公开(公告)号：US06396158B1

公开(公告)日：2002-05-28

申请号：US09340697

申请日：1999-06-29

申请人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian

发明人： Edward O. Travis ,  Aykut Dengi ,  Sejal Chheda ,  Tat-Kwan Yu ,  Mark S. Roberton ,  Ruiqi Tian

IPC分类号： H01L2348

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  Y10S438/926

摘要： Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

摘要翻译： 使用抛光哑特征图案的选择性放置，而不是不加选择地放置抛光哑特征图案。 检查低频（几百微米和更大）和高频（10微米以下）的地形变化。 抛光哑特征图案可以专门针对半导体器件和用于形成半导体器件的抛光条件。 在设计集成电路时，可以预测有源特征的抛光效果。 抛光后，将虚拟特征图案放置在布局中，可以在局部级别（部分但不是全部设备）和更全球级别（所有设备，对应于标线区域的设备）检查平面度 ，甚至整个晶片）。

公开(公告)号：US20080168418A1

公开(公告)日：2008-07-10

申请号：US11651253

申请日：2007-01-08

申请人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

发明人： Omar Zia ,  Nigel Cave ,  Venkat Kolagunta ,  Ruiqi Tian ,  Edward O. Travis

IPC分类号： G06F17/50

CPC分类号： H01L21/84 ,  G06F2217/12 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66651 ,  Y02P90/265

摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

摘要翻译： 提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301） （b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307） 在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。