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1.发明申请METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 有权制造半导体器件的方法和采用这种方法获得的半导体器件公开(公告)号：US20090159938A1
公开(公告)日：2009-06-25
申请号：US12160210
申请日：2007-01-04
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity type which are situated above a buried isolation region (3,4) and with a channel region (5), between the source and drain regions (1,2), of a second conductivity type, opposite to the first conductivity type, and with a gate region (6) separated from the surface of the semiconductor body (12) by a gate dielectric (7) and situated above the channel region (5), and wherein a mesa (M) is formed in the semiconductor body (12) in which the channel region (5) is formed and wherein the source and drain regions (1,2) are formed on both sides of the mesa (M) in a semiconductor region (8) that is formed using epitaxial growth, the source and drain regions (1,2) thereby contacting the channel region (5). According to the invention the semiconductor region (8) is formed contacting the mesa (M) over substantially the whole thickness of the semiconductor region (8) and is formed below the level of the gate dielectric (7). This method is more versatile and the device (10) obtained thus has an improved high-frequency behavior.
摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括场效应晶体管，其中在其表面上设置有源极区（1）的具有衬底（11）的硅（12）的半导体本体， 和位于源极和漏极区域（1,2）之间的第一导电类型的漏极区域（2），其位于掩埋隔离区域（3,4）和沟道区域（5）之上，具有第二导电性 类型，与第一导电类型相反，并且具有通过栅极电介质（7）与半导体本体（12）的表面分离并位于沟道区（5）上方的栅极区（6），并且其中台面 M）形成在其中形成沟道区（5）的半导体本体（12）中，并且在半导体区域（8）中在栅极（M）的两侧形成源区和漏区（1,2） ），源极和漏极区域（1,2）由此与沟道区域（5）接触。 根据本发明，半导体区域（8）形成在半导体区域（8）的基本上整个厚度上与台面（M）接触并形成在栅极电介质（7）的下方。 该方法更通用，因此所获得的装置（10）具有改进的高频行为。
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2.发明申请公开(公告)号：US20100025766A1
公开(公告)日：2010-02-04
申请号：US12519162
申请日：2007-12-10
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/7391 , H01L21/84 , H01L27/1203 , H01L29/41791 , H01L29/785
摘要： A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.
摘要翻译： 一种晶体管器件（10），所述晶体管器件（10）包括衬底（11,14），沿着所述衬底（11,14）上的水平方向排列的鳍状物（3,3A），第一源极/漏极区域 （3,3A）中的第一类型的导电性的第一类型的导电性的第一类型的导电性的第二类型的导电性的第二类型的漏极区域（5） 在第一源极/漏极区域（4）和第二源极/漏极区域（5）之间的鳍片（3,3A）中的沟道区域（33），沟道区域（3）上的栅极绝缘体（6） （33）和栅极绝缘体（6）上的栅极结构（7,8），其中第一源极/漏极区域（4），沟道区域（33）和第二源极/漏极区域（5）的序列 ）沿水平方向排列。
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公开(公告)号：US08362561B2
公开(公告)日：2013-01-29
申请号：US12519162
申请日：2007-12-10
IPC分类号： H01L27/12
CPC分类号： H01L29/7391 , H01L21/84 , H01L27/1203 , H01L29/41791 , H01L29/785
摘要： A transistor device (10), the transistor device (10) comprising a substrate (11, 14), a fin (3, 3A) aligned along a horizontal direction on the substrate (11, 14), a first source/drain region (4) of a first type of conductivity in the fin (3, 3A), a second source/drain region (5) of a second type of conductivity in the fin (3, 3A), wherein the first type of conductivity differs from the second type of conductivity, a channel region (33) in the fin (3, 3A) between the first source/drain region (4) and the second source/drain region (5), a gate insulator (6) on the channel region (33), and a gate structure (7, 8) on the gate insulator (6), wherein the sequence of the first source/drain region (4), the channel region (33) and the second source/drain region (5) is aligned along the horizontal direction.
摘要翻译： 一种晶体管器件（10），所述晶体管器件（10）包括衬底（11,14），沿着所述衬底（11,14）上的水平方向排列的鳍状物（3,3A），第一源极/漏极区域 （3,3A）中的第一类型的导电性的第一类型的导电性的第一类型的导电性的第二类型的导电性的第二类型的漏极区域（5） 在第一源极/漏极区域（4）和第二源极/漏极区域（5）之间的鳍片（3,3A）中的沟道区域（33），沟道区域（3）上的栅极绝缘体（6） （33）和栅极绝缘体（6）上的栅极结构（7,8），其中第一源极/漏极区域（4），沟道区域（33）和第二源极/漏极区域（5）的序列 ）沿水平方向排列。
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公开(公告)号：US09884715B2
公开(公告)日：2018-02-06
申请号：US13116920
申请日：2011-05-26
申请人： Romano Hoofman , Roel Daamen , Youri Victorovitch Ponomarev , Fotopoulou Kyriaki , Matthias Merz , Gilberto Curatola , Anton Tombeur
发明人： Romano Hoofman , Roel Daamen , Youri Victorovitch Ponomarev , Fotopoulou Kyriaki , Matthias Merz , Gilberto Curatola , Anton Tombeur
CPC分类号： B65D79/02 , B65D2203/10 , G01N33/0062 , G01N33/02
摘要： A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer.
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公开(公告)号：US09034637B2
公开(公告)日：2015-05-19
申请号：US12595090
申请日：2008-04-05
IPC分类号： C12M1/34 , C12M1/00 , C12M3/00 , G01R31/26 , H01L21/66 , G01N33/487 , C12Q1/68 , G01N27/414
CPC分类号： G01N33/48721 , C12Q1/6869 , G01N27/414 , C12Q2565/631
摘要： A detector device comprises a substrate (50), a source region (S) and a drain region (D), and a channel region (65) between the source and drain regions. A nanopore (54) passes through the channel region, and connects fluid chambers (56,58) on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.
摘要翻译： 检测器装置包括衬底（50），源极区（S）和漏极区（D）以及在源极和漏极区之间的沟道区（65）。 纳米孔（54）穿过沟道区域，并且连接在衬底的相对侧上的流体室（56,58）。 在流体室，源极和漏极区之间提供电压偏置，并且感测源区和漏区之间的电荷流。 该装置使用纳米孔来限制待测样品（例如核苷酸）靠近传感器。 可以使传感器的尺寸与DNA链中相邻核苷酸的间隔相似。 以这种方式，避免了基于PCR的DNA测序技术的缺点，可以实现单核苷酸分辨率。
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公开(公告)号：US20120228717A1
公开(公告)日：2012-09-13
申请号：US13500405
申请日：2010-11-17
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0629 , H01L27/0814 , H01L27/095 , H01L29/66143 , H01L29/872
摘要： A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors arc formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).
摘要翻译： 在CMOS工艺中制造肖特基二极管的方法包括形成阱，包括用于形成CMOS器件的第一阱（16）和用于形成肖特基器件的第二阱（18）。 然后，在第一阱中形成晶体管，第二阱由保护层（20）和形成于第一阱中的源极和漏极区域的硅化物触点（40）保护。 然后去除保护层，除了在每个第二阱中的接触区域中沉积并蚀刻掉肖特基材料，以在肖特基材料（74）和每个第二阱（18）之间形成肖特基接触。
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7.发明申请公开(公告)号：US20110018065A1
公开(公告)日：2011-01-27
申请号：US12918398
申请日：2009-02-17
IPC分类号： H01L29/775 , H01L27/088 , H01L21/336
CPC分类号： H01L29/7854 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/068 , H01L29/42392 , H01L29/66795 , H01L29/775
摘要： A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20′) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20′); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20′ may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.
摘要翻译： 公开了一种制造半导体器件的方法，其包括提供绝缘载体（10），例如氧化物晶片; 在所述载体（10）上的源极结构（12）和漏极结构（14）之间提供沟道结构（20）; 选择性地去除所述通道结构（20）的一部分，从而在所述通道结构（20）和所述载体（10）之间形成凹部（22）。 将所述装置暴露于退火步骤，使得所述通道结构（20'）获得基本上圆柱形的形状; 形成围绕所述基本上圆柱形的通道结构（20'）的约束层（40）; 生长围绕限制层（40）的氧化物层（50）; 以及形成围绕所述氧化物层（50）的栅极结构（60）。 基本上圆柱形的沟道结构20'可以包括半导体层30.还公开了相应的半导体器件。
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公开(公告)号：US20100044760A1
公开(公告)日：2010-02-25
申请号：US12514940
申请日：2007-11-13
申请人： Gilberto Curatola , Mark Van Dal , Jan Sonsky
发明人： Gilberto Curatola , Mark Van Dal , Jan Sonsky
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/66356
摘要： An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.
摘要翻译： 冲击电离MOSFET形成为从栅极偏移到垂直设置在器件结构内而不是水平的源/漏区之一。 半导体器件包括具有第一掺杂水平的第一源极/漏极区域; 具有第二掺杂水平并且与第一源极/漏极区相反的掺杂剂类型的第二源极/漏极区域，第一和第二源极/漏极区域由具有小于第一和/或第二源极/ 第二掺杂水平; 与所述中间区域电绝缘并设置在所述中间区域上的栅电极，所述第一和第二源极/漏极区域与所述栅电极横向对准; 其中形成与中间区域的边界的第一源极/漏极区域的整个部分与中间区域的顶部垂直地分离。
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公开(公告)号：US09373688B2
公开(公告)日：2016-06-21
申请号：US13100343
申请日：2011-05-04
IPC分类号： H01L29/778 , H01L29/66 , H01L29/423 , H01L29/43 , H01L29/20
CPC分类号： H01L29/42356 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/66462 , H01L29/7786
摘要： A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.
摘要翻译： 常闭晶体管包括III-V族半导体材料的第一区域，第一区域上的III-V族半导体材料的第二区域，第二区域上的III-V族半导体材料的第三区域和至少相邻的栅电极 第三区域的一个侧壁。 第一区域提供晶体管的通道。 第二区域具有比第一区域的带隙大的带隙，并且在通道中产生2-D电子气体（2DEG）。 第二区域介于第一区域和第三区域之间。 第三区域提供晶体管的栅极并且具有足以消耗沟道中的2DEG的厚度，使得晶体管具有正的阈值电压。
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公开(公告)号：US08801917B2
公开(公告)日：2014-08-12
申请号：US13061110
申请日：2009-08-24
IPC分类号： G01N27/327
CPC分类号： G01N27/4148 , G01N27/4145
摘要： The invention relates to a method of determining a charged particle concentration in an analyte (100), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c1, c2, c3, c4), wherein the interface temperature is obtained from a temperature difference between a first interface between a first ion-sensitive dielectric (Fsd) and the analyte (100) and a second interface between a second ion-sensitive dielectric (Ssd) and the analyte (100), and wherein the surface-potential is obtained from a potential difference between a first electrode (Fe) and a second electrode (Se) onto which said first ion-sensitive dielectric (Fsd) and said second ion-sensitive dielectric (Ssd) are respectively provided, And ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c1, c2, c3, c4). This method, which still is a potentiometric electrochemical measurement, exploits the temperature dependency of a surface-potential of an ion-sensitive dielectric in an analyte. The invention further provides an electrochemical sensor for determining a charged particle concentration in an analyte. The invention also provides various sensors which can be used to determine the charged particle concentration, i.e. EGFET's and EIS capacitors.
摘要翻译： 本发明涉及一种测定分析物（100）中带电粒子浓度的方法，所述方法包括以下步骤：i）确定表面电位对界面温度曲线（c1，c2，c3，c3）的至少两个测量点， c4），其中所述界面温度是由第一离子敏感电介质（Fsd）和分析物（100）之间的第一界面与第二离子敏感电介质（Ssd）与分析物之间的第二界面 （100），并且其中所述表面电位由所述第一离子敏感电介质（Fsd）和所述第二离子敏感电介质（Ssd）上的第一电极（Fe）和第二电极（Se）之间的电位差获得， ），和ii）从所述曲线（c1，c2，c3，c4）的至少两个测量点的位置计算带电粒子浓度。 这种仍然是电位电化学测量的方法利用分析物中离子敏感电介质的表面电位的温度依赖性。 本发明还提供了一种用于测定分析物中带电粒子浓度的电化学传感器。 本发明还提供可用于确定带电粒子浓度的各种传感器，即EGFET和EIS电容器。
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