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    Dielectric ceramic composition
    3.
    发明授权
    Dielectric ceramic composition 失效
    介电陶瓷组合物

    公开(公告)号：US5093757A

    公开(公告)日：1992-03-03

    申请号：US649463

    申请日：1991-02-05

    申请人： Kouji Kawakita ,  Suzushi Kimura ,  Hideyuki Okinaka ,  Youichiro Yokotani ,  Mariko Ishikawa

    发明人： Kouji Kawakita ,  Suzushi Kimura ,  Hideyuki Okinaka ,  Youichiro Yokotani ,  Mariko Ishikawa

    IPC分类号： C04B35/472 ,  C04B35/499 ,  H01G4/12

    CPC分类号： H01G4/1254 ,  C04B35/472 ,  C04B35/499

    摘要： The invention relates to a dielectric ceramic composition that can be baked in a short time in the atmosphere, neutral atmosphere or reducing atmosphere at baking temperature of 800.degree. to 1000.degree. C. In the ceramic components expressed by PbTi.sub.X (Mg.sub.1/2 Nb.sub.2/3).sub.Y (Ni.sub.1/2 W.sub.1/2)ZO.sub.3 (where X+Y+Z=1), PbO is added by 1.0 to 25.0 mol % and NiO by 1.0 to 15.0 mol % as subsidiary components, to the temporarily baked powder of the main component dielectric ceramic composition composed in the pentagonal region having the vertices at compositions A, B, C, D, E expressed by numerical values in the following square brackets, in the system of trigonometric coordinates having the vertices at PbTiO.sub.3, Pb(Mg.sub.1/3 Nb.sub.2/3)O.sub.3 and Pb(Ni.sub.1/2 W.sub.1/2)O.sub.3,A is x=2.5, y=9.5, z=2.5;B is x=12.5, y=85.0, z=2.5,C is x=60.0, y=10.0, z=30.0,D is x=40.0, y=10.0, z=50.0,E is x=2.5, y=90.0, z=7.5 (where all untis are mol %)so that a laminate ceramic capacitor or thick film capacitor of large capacity that can be baked densely in a short time at low baking temperature of below 1000.degree. C. will be obtained.

    摘要翻译： 本发明涉及一种可在大气中，中性气氛或还原气氛下在800〜1000℃烘烤温度下短时间烘烤的电介质陶瓷组合物。在PbTiX（Mg1 / 2Nb2 / 3）表示的陶瓷成分中， Y（Ni1 / 2W1 / 2）ZO3（其中X + Y + Z = 1），PbO的添加量为1.0〜25.0mol％，NiO为1.0〜15.0mol％作为辅助成分，添加到主成分 在具有在PbTiO3，Pb（Mg1 / 3Nb2 / Pb）的顶点的三角坐标系统中，在具有由以下方括号中的数值表示的组成A，B，C，D，E的顶点的五边形区域中组成的介电陶瓷组合物， 3）O3和Pb（Ni1 / 2W1 / 2）O3，A为x = 2.5，y = 9.5，z = 2.5; B为x = 12.5，y = 85.0，z = 2.5，C为x = 60.0，y = 10.0，z = 30.0，D为x = 40.0，y = 10.0，z = 50.0，E为x = 2.5，y = 90.0，z = 7.5（其中全部为mol％），从而将获得能够在低于1000℃的低烘烤温度下在短时间内密集烘烤的大容量的层压陶瓷电容器或厚膜电容器。

    Method of manufacturing solid-state electrolytic capacitor
    4.
    发明授权
    Method of manufacturing solid-state electrolytic capacitor 失效
    固态电解电容器的制造方法

    公开(公告)号：US06794260B2

    公开(公告)日：2004-09-21

    申请号：US10415946

    申请日：2003-10-08

    申请人： Tatsuo Fujii ,  Makoto Nakano ,  Yuji Mido ,  Katsumasa Miki ,  Suzushi Kimura

    发明人： Tatsuo Fujii ,  Makoto Nakano ,  Yuji Mido ,  Katsumasa Miki ,  Suzushi Kimura

    IPC分类号： H01L2120

    CPC分类号： H01G9/012 ,  H01G9/15 ,  Y10T29/417

    摘要： A method of manufacturing solid electrolytic capacitors that can be directly connected to semiconductor components and have a faster response to a high frequency as well as a larger capacitance includes: a dielectric forming stage where a valve metal sheet (2) is made porous and a dielectric coating (7) is provided on the porous face (3); an element forming stage where a solid electrolytic layer (8) and a collector layer (10) are formed on the dielectric coating (7); and a terminal forming stage where a connecting terminal (16) for connecting to an external electrode is formed. The element forming stage includes the steps of forming the solid electrolytic layer (8); a forming through-hole electrode (9) in a through-hole (5) that is prepared on the valve metal sheet (2); and forming the collector (10) on the solid electrolytic layer (8).

    摘要翻译： 可以直接连接到半导体部件并且对高频率的响应更快的固体电解电容器的制造方法以及更大的电容包括：电介质形成阶段，其中阀金属片（2）制成多孔的，并且电介质 在多孔面（3）上设置涂层（7） 在电介质涂层（7）上形成固体电解质层（8）和集电极层（10）的元件形成阶段; 以及形成用于连接到外部电极的连接端子（16）的端子形成台。 元件形成阶段包括形成固体电解质层（8）的步骤。 在阀金属片（2）上制备的通孔（5）中形成通孔电极（9）; 以及在所述固体电解质层（8）上形成所述集电体（10）。

    Solid electrolytic capacitor and method of manufacturing the capacitor
    5.
    发明授权
    Solid electrolytic capacitor and method of manufacturing the capacitor 失效
    固体电解电容器及其制造方法

    公开(公告)号：US06775125B2

    公开(公告)日：2004-08-10

    申请号：US10296258

    申请日：2003-01-13

    申请人： Suzushi Kimura ,  Katsumasa Miki ,  Yuji Mido ,  Tatsuo Fujii ,  Hideki Masumi

    发明人： Suzushi Kimura ,  Katsumasa Miki ,  Yuji Mido ,  Tatsuo Fujii ,  Hideki Masumi

    IPC分类号： H01G900

    CPC分类号： H01G9/012 ,  H01G9/15 ,  Y10T29/417

    摘要： A solid electrolytic capacitor having a high capacitance and excellent high frequency response including a valve metal sheet which is made porous, a dielectric layer formed on the porous portion, a solid electrolyte layer formed on the dielectric layer, a collector layer and an electrode exposure area formed on the solid electrolyte layer, and an insulating section electrically insulating the electrode exposure area from the collector layer, in which the electrode exposure area and the collector layer are formed on the same surface of the valve metal sheet.

    摘要翻译： 一种具有高电容性和优异的高频响应的固体电解电容器，包括多孔的阀金属片，形成在多孔部分上的电介质层，形成在电介质层上的固体电解质层，集电层和电极曝光区域 形成在所述固体电解质层上的绝缘部，以及将所述电极曝光区域与所述集电体层电绝缘的绝缘部，所述电极曝光区域和所述集电体层形成在所述阀金属片的同一表面上。

    Method of producing a chip resistor
    6.
    发明授权
    Method of producing a chip resistor 失效
    片式电阻器的制造方法

    公开(公告)号：US06314637B1

    公开(公告)日：2001-11-13

    申请号：US09244965

    申请日：1999-02-05

    申请人： Suzushi Kimura ,  Koji Shimoyama ,  Naotugu Yoneda ,  Keiichi Nakao

    发明人： Suzushi Kimura ,  Koji Shimoyama ,  Naotugu Yoneda ,  Keiichi Nakao

    IPC分类号： H01C1706

    CPC分类号： H01C1/142 ,  H01C7/003 ,  H01C17/006 ,  H01C17/281 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49101

    摘要： The invention relates to a chip resistor which is used as a circuit part for various electric apparatuses. The object of the invention is to realize a low resistance and a low TCR, and also high accuracy and high reliability. In order to achieve the object, a chip resistor is configured so as to have: a substrate; a resistance layer which is formed on at least one face of the substrate and which is made of a copper nickel alloy; upper-face electrode layers which make surface contact with the upper faces of both the end portions of the resistance layer; and end-face electrodes which are formed so as to cover the upper-face electrode layers. Since the bonding between the resistance layer and the upper-face electrode layers is conducted by metal-to-metal bonding, particularly, impurities which may affect the Properties do not exist in the interface. As a result, it is possible to realize a chip resistor which is excellent in heat resistance, and which has a low resistance and a low TCR.

    摘要翻译： 本发明涉及一种片状电阻器，其用作各种电气设备的电路部分。 本发明的目的是实现低电阻和低TCR，并且还具有高精度和高可靠性。 为了实现该目的，芯片电阻器被配置为具有：基板; 电阻层，其形成在所述基板的至少一个面上，并且由铜镍合金制成; 与电阻层的两端部的上表面接触的上表面电极层; 以及形成为覆盖上表面电极层的端面电极。 由于电阻层和上表面电极层之间的结合是通过金属 - 金属键合进行的，特别是界面中不存在影响特性的杂质。 结果，可以实现耐热性优异并且具有低电阻和低TCR的片式电阻器。

    Solid electrolytic capacitor and manufacturing method of the same
    9.
    发明授权
    Solid electrolytic capacitor and manufacturing method of the same 失效
    固体电解电容器及其制造方法相同

    公开(公告)号：US06822849B2

    公开(公告)日：2004-11-23

    申请号：US10703462

    申请日：2003-11-10

    申请人： Katsumasa Miki ,  Tatsuo Fujii ,  Yuji Mido ,  Suzushi Kimura

    发明人： Katsumasa Miki ,  Tatsuo Fujii ,  Yuji Mido ,  Suzushi Kimura

    IPC分类号： H01G900

    CPC分类号： H01G9/15 ,  H01G9/012 ,  H01G9/042 ,  Y10T29/417

    摘要： A solid electrolytic capacitor includes a bulb-metal sheet of which first face has a porous section. A dielectric film, a solid electrolyte layer, and a current-collecting layer are formed in this order on the porous section. On top of the current-collecting layer, a reinforcing plate is bonded. A second face opposite to the first face of the sheet has a connecting terminal conductive to the current-collecting layer. This connecting terminal is coupled to a through-hole electrode which extends through the bulb-metal sheet for appearing outside the second face. The second face has another connecting terminal conductive to the bulb-metal sheet. This structure makes the capacitor thin, and allows the capacitor to increase its stress-resistance and be excellent in responsiveness to a high frequency as well as in mounting convenience.

    摘要翻译： 固体电解电容器包括其第一面具有多孔部分的灯泡金属片。 在多孔部上依次形成电介质膜，固体电解质层和集电层。 在电流收集层的顶部，结合有加强板。 与片材的第一面相对的第二面具有与集电层导电的连接端子。 该连接端子连接到贯穿灯泡金属片的通孔电极，以露出第二面。 第二面具有与灯泡金属片导电的另一连接端子。 这种结构使得电容器变薄，并且允许电容器增加其耐应力，并且对高频响应性以及安装方便性优异。

    Solid electrolytic capacitor and method of manufacturing capacitor
    10.
    发明授权
    Solid electrolytic capacitor and method of manufacturing capacitor 失效

    公开(公告)号：US06775126B2

    公开(公告)日：2004-08-10

    申请号：US10691239

    申请日：2003-10-22

    申请人： Tatsuo Fujii ,  Katsumasa Miki ,  Yuji Mido ,  Suzushi Kimura

    发明人： Tatsuo Fujii ,  Katsumasa Miki ,  Yuji Mido ,  Suzushi Kimura

    IPC分类号： H01G904

    CPC分类号： H01G9/042 ,  H01G9/0425 ,  H01G9/15 ,  Y10T29/417

    摘要： A dielectric layer is formed on a surface of a porous portion formed at least on a surface of a valve metal sheet. A solid electrolyte layer is formed on the dielectric layer, and a collector layer is formed on the solid electrolyte layer. A first insulating portion is formed on an outer periphery of the dielectric layer, and a solid electrolyte layer is formed on a portion of the dielectric layer corresponding to an opening of the first insulating portion. A portion of the solid electrolyte layer is formed on the first insulating portion. A second insulating portion is formed on the first insulating portion and on the outer periphery of the solid electrolyte layer. A collector layer is formed on a surface of the solid electrolyte layer exposed through an opening of the second insulating portion, thus providing a solid electrolytic capacitor. The solid electrolytic capacitor has less current leakage and a high withstand voltage.