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22 条记录 (耗时 0.023 秒)

    Fabrication process of a semiconductor device having an interconnection structure
    1.
    发明授权
    Fabrication process of a semiconductor device having an interconnection structure 失效
    具有互连结构的半导体器件的制造工艺

    公开(公告)号：US5976971A

    公开(公告)日：1999-11-02

    申请号：US685177

    申请日：1996-07-18

    申请人： Shigeru Kinpara ,  Katsunari Hanaoka ,  Ikue Kawashima ,  Kazunori Ito

    发明人： Shigeru Kinpara ,  Katsunari Hanaoka ,  Ikue Kawashima ,  Kazunori Ito

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/44

    CPC分类号： H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002

    摘要： A method of fabricating a semiconductor device includes the steps of forming a contact hole in an insulator layer, filling the contact hole by a conductor material, removing the conductor material from the upper major surface of the insulator layer to form a conductive plug such that the conductive plug fills the contact hole, applying an anisotropic etching process upon the insulator layer, such that the anisotropic etching process acts substantially vertically and selectively to the insulator layer, with an etching rate substantially larger than an etching rate for the conducive plug.

    摘要翻译： 一种制造半导体器件的方法包括以下步骤：在绝缘体层中形成接触孔，用导体材料填充接触孔，从绝缘体层的上主表面去除导体材料，形成导电插塞，使得 导电插塞填充接触孔，对绝缘体层施加各向异性蚀刻工艺，使得各向异性蚀刻工艺基本上垂直且选择性地对绝缘体层施加蚀刻速率，其蚀刻速率明显大于导电插塞的蚀刻速率。

    Semiconductor integrated circuit device and a method of manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit device and a method of manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US5589712A

    公开(公告)日：1996-12-31

    申请号：US349033

    申请日：1994-12-02

    申请人： Ikue Kawashima ,  Katsunari Hanaoka

    发明人： Ikue Kawashima ,  Katsunari Hanaoka

    IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L21/44

    CPC分类号： H01L21/76838 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915 ,  Y10S257/924

    摘要： A semiconductor integrated circuit device includes a substrate formed with semiconductor elements and a metal wiring having a laminated structure and provided on the substrate. The metal wiring includes a first layer including aluminum as a main component, and a second layer formed on the first layer. The second layer includes titanium and nitrogen as main components. The second layer includes more titanium than nitrogen in number of atoms. A third layer may be formed between the first and second layers. The third layer includes a compound of aluminum and titanium as a main component. A fourth layer may further be formed between the second and third layers. The fourth layer includes titanium as a main component and is free of aluminum.

    摘要翻译： 半导体集成电路器件包括形成有半导体元件的基板和具有叠层结构并设置在基板上的金属布线。 金属布线包括以铝为主要成分的第一层和形成在第一层上的第二层。 第二层包括钛和氮作为主要成分。 第二层包括比氮原子多的钛。 可以在第一层和第二层之间形成第三层。 第三层包括以铝和钛为主要成分的化合物。 可以在第二层和第三层之间进一步形成第四层。 第四层包括钛作为主要成分并且不含铝。

    Method for forming ohmic contact
    5.
    发明授权
    Method for forming ohmic contact 失效
    形成欧姆接触的方法

    公开(公告)号：US6001720A

    公开(公告)日：1999-12-14

    申请号：US726862

    申请日：1996-10-04

    申请人： Katsunari Hanaoka ,  Ikuo Shiota

    发明人： Katsunari Hanaoka ,  Ikuo Shiota

    IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/28 ,  H01L21/31

    CPC分类号： H01L21/28512 ,  H01L21/2652 ,  Y10S438/95

    摘要： A method for forming ohmic contact has the steps of a) a process for forming an insulating film having a predetermined thickness on a diffusive layer formed on a semiconductor substrate; b) a process for forming a mask on the insulating film; the mask having a small selective ratio with respect to the insulating film and having an opening portion for a contact hole; c) a process for implanting ions into the diffusive layer through the opening portion; d) a process for taking heat treatment to electrically activate the implanted ions; e) a process for completely removing the mask and forming the contact hole by simultaneously etching the mask and the insulating film exposed through the opening portion of the mask; and f) a process for making an electrode come in ohmic contact with the semiconductor substrate exposed from the formed contact hole. In this method, the ohmic contact is formed with high accuracy with respect to a fine contact hole.

    摘要翻译： 一种形成欧姆接触的方法具有以下步骤：a）在半导体衬底上形成的扩散层上形成具有预定厚度的绝缘膜的工艺; b）在绝缘膜上形成掩模的工艺; 所述掩模相对于所述绝缘膜具有小的选择比并且具有用于接触孔的开口部分; c）通过所述开口部分将离子注入到扩散层中的方法; d）进行热处理以电激活注入离子的方法; e）通过同时蚀刻掩模和通过掩模的开口部分暴露的绝缘膜来完全去除掩模并形成接触孔的工艺; 以及f）用于使电极与形成的接触孔露出的半导体衬底欧姆接触的工艺。 在该方法中，相对于微细接触孔，高精度地形成欧姆接触。

    Semiconductor device with contact hole
    6.
    发明授权
    Semiconductor device with contact hole 失效
    具有接触孔的半导体器件

    公开(公告)号：US5656841A

    公开(公告)日：1997-08-12

    申请号：US545398

    申请日：1995-10-19

    申请人： Hirofumi Watanabe ,  Kaihei Isshiki ,  Tetsurou Tanigawa ,  Yasuyuki Shindou ,  Katsunari Hanaoka

    发明人： Hirofumi Watanabe ,  Kaihei Isshiki ,  Tetsurou Tanigawa ,  Yasuyuki Shindou ,  Katsunari Hanaoka

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/11

    CPC分类号： H01L21/768 ,  H01L2924/0002 ,  Y10S257/903

    摘要： In a manufacturing method of a semiconductor device, a gate insulating film is grown in an active region. Thereafter, an N-type polysilicon film is formed on the gate insulating film and is patterned so that a gate electrode and a polysilicon electrode are formed. Next, arsenic ions are implanted onto entire faces of the gate and polysilicon electrodes so that a source-drain region is formed on a substrate. An interlayer insulating film is then formed on an entire face of the source-drain region, etc. Thereafter, a contact hole is formed on a drain region in a position in which the drain region partially overlaps the polysilicon electrode. A surface portion of the polysilicon electrode is exposed into the contact hole. Thereafter, phosphoric ions are implanted through the contact hole with the interlayer insulating film as a mask. The implanted ions are thermally processed to activate these implanted ions. Thereafter, metal wiring is formed. Thus, resistance of a common contact having s three-dimensional structure is reduced.

    摘要翻译： 在半导体器件的制造方法中，在有源区域中生长栅极绝缘膜。 此后，在栅极绝缘膜上形成N型多晶硅膜，并形成栅电极和多晶硅电极。 接下来，将砷离子注入到栅极和多晶硅电极的整个表面上，从而在衬底上形成源极 - 漏极区域。 然后在源极 - 漏极区域的整个表面上形成层间绝缘膜等。此后，在漏极区域与多晶硅电极部分重叠的位置处的漏极区域上形成接触孔。 多晶硅电极的表面部分露出到接触孔中。 此后，通过与层间绝缘膜作为掩模的接触孔注入磷酸根离子。 将注入的离子热处理以激活这些注入的离子。 此后，形成金属布线。 因此，具有三维结构的普通接触的电阻降低。

    VERTICAL CAVITY SURFACE EMITTING LASER ELEMENT, VERTICAL CAVITY SURFACE EMITTING LASER ARRAY, OPTICAL SCANNING DEVICE, AND IMAGE FORMING APPARATUS
    8.
    发明申请
    VERTICAL CAVITY SURFACE EMITTING LASER ELEMENT, VERTICAL CAVITY SURFACE EMITTING LASER ARRAY, OPTICAL SCANNING DEVICE, AND IMAGE FORMING APPARATUS 有权
    垂直孔表面发射激光元件，垂直孔表面发射激光阵列，光学扫描装置和图像形成装置

    公开(公告)号：US20110316961A1

    公开(公告)日：2011-12-29

    申请号：US13147239

    申请日：2009-12-22

    申请人： Katsunari Hanaoka

    发明人： Katsunari Hanaoka

    IPC分类号： B41J2/47 ,  H01S5/34 ,  H01S5/42 ,  H01S5/183

    CPC分类号： B41J2/442 ,  B41J2/455 ,  B41J2/473 ,  H01S5/18311 ,  H01S5/18352 ,  H01S5/2086 ,  H01S5/423

    摘要： A disclosed vertical cavity surface emitting laser element includes a substrate, a laminated body sandwiching a semiconductor active layer with an upper reflecting mirror and a lower reflecting mirror, a lower electrode, and an upper electrode. The laser element emits laser light in a direction perpendicular to the surface of the substrate when an electric current is supplied between the upper electrode and the lower electrode. The laser element further includes a selective oxidation layer in the upper reflecting mirror having a current blocking structure made of an oxidized region and an unoxidized region, and a detectable portion formed on a side surface of a mesa structure shaped by the upper reflecting mirror including the selective oxidation layer and the active layer, thereby enabling detecting the position of the selective oxidation layer from a top of the laminated body in a depth direction of the laminated body.

    摘要翻译： 所公开的垂直腔表面发射激光器元件包括基板，夹着半导体有源层与上反射镜和下反射镜，下电极和上电极的层叠体。 当在上电极和下电极之间提供电流时，激光元件在垂直于衬底表面的方向上发射激光。 激光元件还包括在上反射镜中具有由氧化区域和非氧化区域构成的电流阻挡结构的选择性氧化层，以及形成在由上反射镜形成的台面结构的侧表面上的可检测部分， 选择性氧化层和有源层，从而能够在层叠体的深度方向上从层叠体的顶部检测选择氧化层的位置。

    Process for producing stamper of multi-valued ROM disc, apparatus for producing the same, and resulting disc
    9.
    发明授权
    Process for producing stamper of multi-valued ROM disc, apparatus for producing the same, and resulting disc 失效
    用于制造多值ROM盘的压模的方法，用于制造它的装置以及所得到的盘

    公开(公告)号：US07990838B2

    公开(公告)日：2011-08-02

    申请号：US11579816

    申请日：2005-05-18

    申请人： Katsunari Hanaoka ,  Hiroshi Miura

    发明人： Katsunari Hanaoka ,  Hiroshi Miura

    IPC分类号： G11B7/26

    CPC分类号： G11B7/24088 ,  G11B7/263

    摘要： The present invention provides a process for producing inexpensively and effectively a stamper utilized for producing multi-valued ROM discs, which comprises: (i) irradiating a light onto a laminate, thereby producing reacted portions within a thermo reactive layer, (ii) maintaining the reacted portions, which are produced by irradiating the light, within the thermo reactive layer, (iii) maintaining an optical absorption layer under the reacted portions, (iv) maintaining a substrate under the reacted portions, and (v) removing the maintained optical absorption layer and the maintained thermo reactive layer, wherein the laminate comprises the optical absorption layer and the thermo reactive layer on the substrate, the optical absorption layer and the thermo reactive layer are disposed adjacently.

    摘要翻译： 本发明提供了一种用于生产廉价且有效的用于生产多值ROM盘的压模的方法，其包括：（i）将光照射到层压板上，从而在热反应层内产生反应部分，（ii）保持 （iii）在反应部分下保持光吸收层，（iv）在反应部分下维持基底，和（v）除去维持的光吸收 层和维持的热反应层，其中层压体包括基底上的光吸收层和热反应层，光吸收层和热反应层相邻设置。